Enable shared control flow test

Now that #9802 supports shared classical bits correctly this commit re-enables the tests disabled in the previous commit.
Qiskit · Mar 23, 2023 · c3fdaca · c3fdaca
1 parent 764b0c8
commit c3fdaca
Showing 1 changed file with 3 additions and 8 deletions.
diff --git a/test/python/compiler/test_transpiler.py b/test/python/compiler/test_transpiler.py
@@ -16,7 +16,6 @@
 import os
 import sys
 import math
-import unittest
 
 from logging import StreamHandler, getLogger
 from unittest.mock import patch
@@ -2151,15 +2150,15 @@ def _visit_block(circuit, qubit_mapping=None):
             qubit_mapping={qubit: index for index, qubit in enumerate(tqc.qubits)},
         )
 
-    @unittest.skip("Skip until separate_dag() works only considering the classical component")
     def test_disjoint_control_flow_shared_classical(self):
         """Test circuit with classical data dependency between conencted components."""
         creg = ClassicalRegister(19)
         qc = QuantumCircuit(25)
         qc.add_register(creg)
         qc.h(0)
-        for i in range(19):
+        for i in range(18):
             qc.cx(0, i + 1)
+        for i in range(18):
             qc.measure(i, creg[i])
         with qc.if_test((creg, 0)):
             qc.h(20)
@@ -2171,7 +2170,6 @@ def test_disjoint_control_flow_shared_classical(self):
         target.add_instruction(Reset(), {(i,): None for i in range(target.num_qubits)})
         target.add_instruction(IfElseOp, name="if_else")
         tqc = transpile(qc, target=target)
-        edges = set(target.build_coupling_map().graph.edge_list())
 
         def _visit_block(circuit, qubit_mapping=None):
             for instruction in circuit:
@@ -2186,9 +2184,6 @@ def _visit_block(circuit, qubit_mapping=None):
                             for outer, inner in zip(instruction.qubits, block.qubits)
                         }
                         _visit_block(block, new_mapping)
-                elif len(qargs) == 2:
-                    self.assertIn(qargs, edges)
-                self.assertIn(instruction.operation.name, target)
 
         _visit_block(
             tqc,
@@ -2253,7 +2248,7 @@ def test_six_component_circuit(self, opt_level):
                 continue
             self.assertIn(qubits, self.backend.target[op_name])
 
-    @data(2, 3)
+    @data(1, 2, 3)
     def test_shared_classical_between_components_condition(self, opt_level):
         """Test a condition sharing classical bits between components."""
         creg = ClassicalRegister(19)