MPL drawer extended for drawing circuits with single classical bit conditioning #6259
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TharrmashasthaPV
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qiskit/visualization/matplotlib.py
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| if cond_is_bit and self._cregbundle: | ||
| cond_reg = self._bit_locations[op.condition[0]]["register"] | ||
| ctrl_bit = self._bit_locations[op.condition[0]]["index"] | ||
| label = "%s_%s=%s" % (cond_reg.name, ctrl_bit, hex(val)) |
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Does it make sense to do this in math notation "$%s_%s$=%s" so that is comes out a subscript instead of an underscore?
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Subscript is a good idea. But I just feel that the subscript would be very small. It would look something like this
If this is still fine, I think subscript is more preferable since it also saves some space.
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Agreed it is small. Since it should be zoomable on most devices, I'm ok with it. Probably one for final reviewer to decide.
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I think better to leave it with the underscore so it is more accessible for users with limited eyesight, devices without zoom capabilities, screenshots etc.
qiskit/visualization/matplotlib.py
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| for index, cbit in enumerate(self._clbit): | ||
| if self._bit_locations[cbit]["register"] == node.op.condition[0]: | ||
| mask |= 1 << index | ||
| if cond_is_bit: | ||
| for index, cbit in enumerate(self._clbit): | ||
| if cbit == node.op.condition[0]: |
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I think you have an extra for loop at line 869.
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Ah. Thanks for pointing to out. Fixed it in 1d9c58f .
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Changelog: Bugfix
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hey @TharrmashasthaPV when I run the binder tests at https://mybinder.org/v2/gh/TharrmashasthaPV/qiskit-terra/issue1160mpl?urlpath=apps/test/ipynb/mpl_tester.ipynb i see a few failures that should be fixed before this gets merged in 😄 |
Oh. Sorry for that. I have replaced the incorrect reference image with the right ones in 7dc2d59. I also made a small change to have hex under the control bit even for single bit conditions when cregbundle=False (This was not there in the previous commit ) like below:
and brought back the underscore.
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Summary
Fixes part of #6475 . This PR extends the ability of the current mpl drawer to draw circuits that contain gates or instructions that are conditioned on a single classical bit.
Details and comments
This PR follows #6018 . #6018 breaks the mpl drawer when drawing circuits that contain instructions with single bit conditioning. This is an attempt at fixing this error. Two tests have been added. Examples of the mpl drawing are as below.
With cregbundle=True:
With cregbundle=False:
