QEP: Qucs compact device modelling with MAPP, ADMS VerilogA and subcircuits

QEP: Qucs compact device modelling with MAPP, ADMS Verilog A models and subcircuits

Author: Mike Brinson
Status: Draft
Created: 29.12.2014

Background to the proposal

This is a proposal which concerns the development of new Qucs device and circuit simulation models based on subcircuits and synthesised code blocks constructed using the recently released Berkeley GPL “Model and Algorithm Prototyping Platform” and the Qucs ADMS/Verilog-A C++ model synthesizer. Model construction has been a central theme of Qucs development since the original version of the simulation software was published by sourceforge. However, the past approach has been rather piecemeal, unstructured and often poorly documented. The work introduced in this proposal will attempt to improve the past device modelling procedures, providing in their place a structured, and well documented, modelling route which should be easily understood by all Qucs user from beginner to advanced model developer.

Overall Aims

1. To introduce a structured procedure for constructing Qucs device and circuit models.
2. To demonstrate good modelling practice through a number of modelling examples of increasing complexity.
3. To establish a Qucs standard for the documentation describing device and circuit model properties and application.

The sequence of the work proposed

1. MAPP was originally developed with MATLAB  but should work with Octave. However, initial tests showed that differences in the performance of a number of MATLAB/Octave functions caused compatibility problems. Stage one of this proposal has been to trace these compatibility problems, correct them and interface MAPP to the Qucs GUI.
   This stage has now been completed and the traced problems reported to the MAPP team at Berkeley.

2. Stage two will follow directly from 1 in that it will concentrate on providing documentation on how to use MAPP with Qucs.

3. Stage 3 will start the process of developing Qucs models using MAPP. A series of simple examples will be employed to demonstrate the modelling sequence. All stages will be documented for future reference.

4. Stage 4 will concentrate on using MAPP to model RF circuit blocks constructed from built-in MAPP models. Example circuit models, MAPP simulation and post simulation data processing will be employed to establish confidence in the MAPP/Qucs modelling process. All example models and simulations will be documented for future reference.

5. Stage 4 will introduce modelling of semiconductor devices. Again a series of examples and a range of documentation will report the results from this stage.

6. At this point in the modelling project the models developed and evaluated by the MAPP software will be converted to Verilog-A code and compiled and tested using the Qucs/ADMS model construction system. A range of suitable example models and documentation will be used to document this stages results.

7. Provided the previous stages were successful an attempt will be made to describe and document a structured model development process for Qucs.

8. On-going long term development of models for use in Qucs simulation.