CPU SAML21: fix timers frequency when using slow clocks

[ant9000]

My recently merged PR #16433 introduces a bug: when OSC16M is not running at 16MHz, the timer clock SAM0_GCLK_8MHZ is no longer correct.

I've renamed SAM0_GCLK_8MHZ as SAM0_GCLK_TIMER, and compute it as 4MHz or 8MHz depending on the frequency of the core clock - CLOCK_CORECLOCK at 4MHz or at 12MHz result in SAM0_GCLK_TIMER at 4MHz, all other available core clocks still produce the original 8MHz one.

[benpicco]

Looks good to me - just a minor thing: please prefix the commits with the subsystem they are touching, so

• cpu/saml21: fix timer skew for slow clocks
• boards: use SAM0_GCLK_TIMER for saml21 boards

[dylad]

One comment otherwise looks good.

[dylad]

LGTM, tested on saml21-xpro with tests/xtimer_usleep

@benpicco any last word ?

[benpicco]

There is a case for using OSC16M instead of the DFLL - the buck converter can only be enabled if no DPLL/DFLL is used (see errata sheet).
But I can do that as a follow-up.

[ant9000]

There is a case for using OSC16M instead of the DFLL - the buck converter can only be enabled if no DPLL/DFLL is used (see errata sheet).
But I can do that as a follow-up.

If I am not mistaken, that errata should be already taken care of, in _set_active_mode_vreg; but if you really need a 48MHz clock (for USB, for instance), you just can't work around enabling DFLL48M (at present, DPLL96M is not supported at all in RIOT).

[dylad]

ACK.
Re-tested on SAML21. Looks good so far.

[dylad]

Here we go.

[ant9000]

Thanks a lot!