Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

cpu/saml1x: avoid the use of bitfield in register calls #20710

Merged
merged 1 commit into from
May 30, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 7 additions & 8 deletions cpu/saml1x/cpu.c
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@
| OSC32KCTRL_OSC32K_ENABLE;

/* Wait OSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.OSC32KRDY) {}
while (!(OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_OSC32KRDY)) {}
#endif /* INTERNAL_OSC32_SOURCE */
}

Expand All @@ -78,7 +78,7 @@
| OSC32KCTRL_XOSC32K_ENABLE;

/* Wait XOSC32K Ready */
while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {}
while (!(OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY)) {}
#endif
}

Expand Down Expand Up @@ -140,14 +140,15 @@
#ifdef MODULE_PERIPH_RTC_RTT
| MCLK_APBAMASK_RTC
#endif
;

Check warning on line 143 in cpu/saml1x/cpu.c

View workflow job for this annotation

GitHub Actions / static-tests

semicolon is isolated from other tokens

/* Disable the RTC module to prevent synchronization issues during CPU init
if the RTC was running from a previous boot (e.g wakeup from backup)
as the module will be re-init during the boot process */
if (RTC->MODE2.CTRLA.bit.ENABLE && IS_ACTIVE(MODULE_PERIPH_RTC_RTT)) {
if ((RTC->MODE2.CTRLA.reg & RTC_MODE2_CTRLA_ENABLE) &&
IS_ACTIVE(MODULE_PERIPH_RTC_RTT)) {
while (RTC->MODE2.SYNCBUSY.reg) {}
RTC->MODE2.CTRLA.bit.ENABLE = 0;
RTC->MODE2.CTRLA.reg &= ~ RTC_MODE2_CTRLA_ENABLE;
while (RTC->MODE2.SYNCBUSY.reg) {}
}
/* Software reset the GCLK module to ensure it is re-initialized correctly */
Expand All @@ -156,16 +157,14 @@
while (GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) {}

PM->PLCFG.reg = PM_PLCFG_PLSEL_PL2;
while (!PM->INTFLAG.bit.PLRDY) {}
while (!(PM->INTFLAG.reg & PM_INTFLAG_PLRDY)) {}

MCLK->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
_NVMCTRL->CTRLB.reg |= NVMCTRL_CTRLB_RWS(1);
MCLK->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;

/* set OSC16M to 16MHz */
OSCCTRL->OSC16MCTRL.bit.FSEL = 3;
OSCCTRL->OSC16MCTRL.bit.ONDEMAND = 0;
OSCCTRL->OSC16MCTRL.bit.RUNSTDBY = 0;
OSCCTRL->OSC16MCTRL.reg = (OSCCTRL_OSC16MCTRL_FSEL_16 | OSCCTRL_OSC16MCTRL_ENABLE);

_osc32k_setup();
_xosc32k_setup();
Expand Down
4 changes: 2 additions & 2 deletions cpu/saml1x/periph/pm.c
Original file line number Diff line number Diff line change
Expand Up @@ -43,9 +43,9 @@ void pm_set(unsigned mode)
}

/* write sleep configuration */
PM->SLEEPCFG.bit.SLEEPMODE = _mode;
PM->SLEEPCFG.reg = _mode;
/* make sure value has been set */
while (PM->SLEEPCFG.bit.SLEEPMODE != _mode) {}
while ((PM->SLEEPCFG.reg & PM_SLEEPCFG_SLEEPMODE_Msk) != _mode) {}

sam0_cortexm_sleep(deep);
}
Loading