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@RoaLogic

Roa Logic BV

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  1. RV12 RV12 Public

    RISC-V CPU Core

    SystemVerilog 287 50

  2. ahb3lite_interconnect ahb3lite_interconnect Public

    AHB3-Lite Interconnect

    SystemVerilog 81 27

  3. ahb3lite_apb_bridge ahb3lite_apb_bridge Public

    Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

    SystemVerilog 41 19

  4. plic plic Public

    Platform Level Interrupt Controller

    SystemVerilog 35 14

  5. Hamming-ECC Hamming-ECC Public

    Hamming ECC Encoder and Decoder to protect memories

    SystemVerilog 28 23

  6. ahb3lite_memory ahb3lite_memory Public

    Multi-Technology RAM with AHB3Lite interface

    SystemVerilog 20 16

Repositories

Showing 10 of 31 repositories
  • virtualdevboard Public

    Graphical Virtual SoC Development Board Builder using Verilator

    RoaLogic/virtualdevboard’s past year of commit activity
    C++ 0 BSD-3-Clause 0 0 0 Updated Nov 13, 2024
  • Verilator-simulation Public

    Collection of C++ classes to create Verilator Testbenches

    RoaLogic/Verilator-simulation’s past year of commit activity
    C++ 2 GPL-3.0 0 0 0 Updated Nov 2, 2024
  • Hamming-ECC Public

    Hamming ECC Encoder and Decoder to protect memories

    RoaLogic/Hamming-ECC’s past year of commit activity
    SystemVerilog 28 23 0 2 Updated Oct 7, 2024
  • yosys Public Forked from YosysHQ/yosys

    Yosys Open SYnthesis Suite

    RoaLogic/yosys’s past year of commit activity
    C++ 0 ISC 903 0 1 Updated Sep 24, 2024
  • RV12 Public

    RISC-V CPU Core

    RoaLogic/RV12’s past year of commit activity
    SystemVerilog 287 50 4 0 Updated Jun 8, 2024
  • rv_soc Public

    Roa Logic RISC-V SoC

    RoaLogic/rv_soc’s past year of commit activity
    SystemVerilog 1 2 0 0 Updated May 21, 2024
  • ahb3lite_sdram_ctrl Public

    AHB3 Lite SDRAM Controller

    RoaLogic/ahb3lite_sdram_ctrl’s past year of commit activity
    SystemVerilog 1 1 0 0 Updated May 21, 2024
  • apb4_uart16550 Public

    16550 UART with APB4 Interface

    RoaLogic/apb4_uart16550’s past year of commit activity
    SystemVerilog 4 BSD-2-Clause 1 0 0 Updated May 14, 2024
  • ahb3lite_interconnect Public

    AHB3-Lite Interconnect

    RoaLogic/ahb3lite_interconnect’s past year of commit activity
    SystemVerilog 81 27 1 0 Updated May 10, 2024
  • adv_dbg_if Public

    Universal Advanced JTAG Debug Interface

    RoaLogic/adv_dbg_if’s past year of commit activity
    SystemVerilog 17 11 0 0 Updated May 10, 2024
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