V2.5 lx2160acex7 - Backport snoop-delayed exclusive handling on A72 cores

include/lib/cpus/aarch32/cortex_a72.h

@@ -37,16 +37,21 @@
 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA		(ULL(1) << 49)
 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI			(ULL(1) << 44)
 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH		(ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP	(ULL(1) << 31)
 
 /*******************************************************************************
  * L2 Control register specific definitions.
  ******************************************************************************/
 #define CORTEX_A72_L2CTLR				p15, 1, c9, c0, 2
 
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE	(ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE	(ULL(1) << 20)
+
 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT	U(0)
 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT		U(6)
 
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES		U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES		U(0x3)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES		U(0x1)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES		U(0x2)
 

include/lib/cpus/aarch64/cortex_a72.h

@@ -37,6 +37,7 @@
 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA			(ULL(1) << 49)
 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI			(ULL(1) << 44)
 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH		(ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP		(ULL(1) << 31)
 
 /*******************************************************************************
  *  L2 Auxiliary Control register specific definitions.
@@ -57,6 +58,9 @@
  ******************************************************************************/
 #define CORTEX_A72_L2CTLR_EL1				S3_1_C11_C0_2
 
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE	(ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE	(ULL(1) << 20)
+
 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT	U(0)
 #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT		U(5)
 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT		U(6)
@@ -65,6 +69,7 @@
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK		U(0x7)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK		U(0x7)
 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES		U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES		U(0x3)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES		U(0x1)
 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES		U(0x2)
 

plat/nxp/common/aarch64/ls_helpers.S

@@ -6,8 +6,8 @@
  */
 
 #include <asm_macros.S>
+#include <cortex_a72.h>
 #include <drivers/console.h>
-#include <lib/cpus/aarch64/cortex_a72.h>
 
 #include <platform_def.h>
 
@@ -23,6 +23,7 @@
 	.globl _disable_ldstr_pfetch_A53
 	.globl _disable_ldstr_pfetch_A72
 	.global	_set_smmu_pagesz_64
+	.global _enable_delay_exclusive_snoop_A72
 
 	/* int plat_crash_console_init(void)
 	 * Function to initialize the crash console
@@ -192,3 +193,22 @@ func _set_smmu_pagesz_64
 
 	ret
 endfunc _set_smmu_pagesz_64
+
+/*
+ * Function enables snoop-delayed exclusive handling on A72 cores
+ */
+func _enable_delay_exclusive_snoop_A72
+        mrs     x0, CORTEX_A72_CPUACTLR_EL1
+        tst     x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+        b.eq    1f
+        b       2f
+.align 6
+1:
+        dsb     sy
+        isb
+        orr     x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+        msr     CORTEX_A72_CPUACTLR_EL1, x0
+        isb
+2:
+        ret
+endfunc _enable_delay_exclusive_snoop_A72

plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S

@@ -37,6 +37,7 @@ func plat_reset_handler
 	bl  apply_platform_errata
 
 #if defined(IMAGE_BL31)
+	bl _enable_delay_exclusive_snoop_A72
 	ldr x0, =POLICY_SMMU_PAGESZ_64K
 	cbz x0, 1f
 	/* Set the SMMU page size in the sACR register */

plat/ti/k3/board/j784s4/board.mk

@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL32_BASE ?= 0x9e800000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x80080000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x82000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
+
+# Define sec_proxy usage as the full prioritized communication scheme
+K3_SEC_PROXY_LITE	:=	0
+$(eval $(call add_define,K3_SEC_PROXY_LITE))
+
+# Use a 4 cycle data RAM latency for J784s4
+K3_DATA_RAM_4_LATENCY	:=	1
+$(eval $(call add_define,K3_DATA_RAM_4_LATENCY))
+
+# Delay snoop exclusive handling for J784s4
+K3_EXCLUSIVE_SNOOP_DELAY	:=	1
+$(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY))
+
+# System coherency is managed in hardware
+USE_COHERENT_MEM	:=	1
+
+PLAT_INCLUDES		+=	\
+				-Iplat/ti/k3/board/j784s4/include	\

plat/ti/k3/common/k3_helpers.S

@@ -105,8 +105,32 @@ func plat_reset_handler
 	/* Cortex-A72 specific settings */
 a72:
 	mrs x0, CORTEX_A72_L2CTLR_EL1
-	orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#if K3_DATA_RAM_4_LATENCY
+	/* Set L2 cache data RAM latency to 4 cycles */
+	orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \
+			CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#else
+	/* Set L2 cache data RAM latency to 3 cycles */
+	orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
+			CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#endif
+	/* Enable L2 ECC and parity with inline data */
+	orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
+	orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
 	msr CORTEX_A72_L2CTLR_EL1, x0
+
+	mrs x0, CORTEX_A72_L2ACTLR_EL1
+	/* Enable L2 UniqueClean evictions with data */
+	orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
+	msr CORTEX_A72_L2ACTLR_EL1, x0
+
+#if K3_EXCLUSIVE_SNOOP_DELAY
+	mrs	x0, CORTEX_A72_CPUACTLR_EL1
+	/* Set Snoop-delayed exclusive handling */
+	orr	x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+	msr	CORTEX_A72_CPUACTLR_EL1, x0
+#endif
+
 	isb
 	ret
 endfunc plat_reset_handler