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V2.5 lx2160acex7 - Backport snoop-delayed exclusive handling on A72 cores #1

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@ndoo ndoo commented Oct 8, 2024

Backport patch from @jnettlet on Discord to v2.5 tag.

Cherry-pick the commit with the definition of CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP in ‎include/lib/cpus/aarch32/cortex_a72.h from mainline.

@ndoo ndoo marked this pull request as draft October 8, 2024 15:37
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ndoo commented Oct 8, 2024

Converting to draft as it does not solve rcu stalls on OpenZFS workloads.

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@ndoo ndoo force-pushed the v2.5-lx2160acex7 branch 2 times, most recently from aa32070 to 728a100 Compare October 9, 2024 03:16
glneo added 3 commits October 9, 2024 18:54
The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883
The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c
Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9
@ndoo ndoo force-pushed the v2.5-lx2160acex7 branch 14 times, most recently from 34dd1a0 to 4ec6fad Compare October 9, 2024 13:18
Signed-off-by: Andrew Yong <me@ndoo.sg>
@ndoo ndoo force-pushed the v2.5-lx2160acex7 branch from 4ec6fad to 22cd7f4 Compare October 9, 2024 15:09
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2 participants