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Merge branch 'watchpoint' into dev
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# Conflicts:
#	src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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Dolu1990 committed Apr 4, 2024
2 parents 0e4032c + 2cd19c8 commit 26e38b3
Showing 1 changed file with 9 additions and 2 deletions.
11 changes: 9 additions & 2 deletions src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
Original file line number Diff line number Diff line change
Expand Up @@ -267,7 +267,9 @@ object VexRiscvSmpClusterGen {
withInstructionCache : Boolean = true,
forceMisa : Boolean = false,
forceMscratch : Boolean = false,
privilegedDebug : Boolean = false,
privilegedDebug: Boolean = false,
privilegedDebugTriggers: Int = 2,
privilegedDebugTriggersLsu: Boolean = false,
csrFull : Boolean = false
) = {
assert(iCacheSize/iCacheWays <= 4096, "Instruction cache ways can't be bigger than 4096 bytes")
Expand All @@ -276,7 +278,12 @@ object VexRiscvSmpClusterGen {

val misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}${if(rvc) "c" else ""}${if(withSupervisor) "su" else ""}")
val csrConfig = if(withSupervisor){
var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(withPrivilegedDebug = privilegedDebug)
var c = CsrPluginConfig.openSbi(mhartid = hartId, misa = misa).copy(
utimeAccess = CsrAccess.READ_ONLY,
withPrivilegedDebug = privilegedDebug,
debugTriggers = privilegedDebugTriggers,
debugTriggersLsu = privilegedDebugTriggersLsu
)
if(csrFull){
c = c.copy(
mcauseAccess = CsrAccess.READ_WRITE,
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