Fix FpuAddSharedPlugin packPort.cmd.at usage

SpinalHDL · Sep 25, 2024 · 0e3bb7f · 0e3bb7f
1 parent 7f167a5
commit 0e3bb7f
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuAddSharedPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuAddSharedPlugin.scala
@@ -117,7 +117,7 @@ class FpuAddSharedPlugin(lane: ExecuteLanePlugin,
  )
 
  val onPack = new pip.Area(packAt) {
- val mask = inserter.GROUP_OH.andMask(isValid)
+ val mask = (inserter.GROUP_OH & uopsAt.map(e => lane.execute(e._1+packAt).isValid).asBits)
 
  packPort.cmd.at := mask
  packPort.cmd.value.mode := adder.result.RESULT.mode

diff --git a/src/main/scala/vexiiriscv/execute/fpu/FpuPackerPlugin.scala b/src/main/scala/vexiiriscv/execute/fpu/FpuPackerPlugin.scala
@@ -97,7 +97,7 @@ class FpuPackerPlugin(val lane: ExecuteLanePlugin,
  Decode.UOP_ID := reader(_.uopId)
  valid := reader.oh.orR
  val GROUP_OH = Payload(Bits(uopsAt.size bits))
- assert(CountOne(GROUP_OH) <= 1)
+ assert(CountOne(GROUP_OH) <= 1, "Packing GROUP_OH failure")
  for((at, sel) <- (uopsAt.keys, GROUP_OH.asBools).zipped){
  sel := (for(port <- ports; (portAt, i) <- port.cmd.ats.zipWithIndex; if portAt == at) yield port.cmd.at(i)).orR
  }