ensure mtvec/mepc lsb are clear

trap on privileged read-only writes
SpinalHDL · Jan 5, 2024 · 1990468 · 1990468
1 parent 30549b8
commit 1990468
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Showing 4 changed files with 20 additions and 13 deletions.
diff --git a/ext/NaxSoftware b/ext/NaxSoftware
diff --git a/ext/riscv-isa-sim b/ext/riscv-isa-sim
diff --git a/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala b/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala
@@ -51,7 +51,7 @@ class CsrAccessPlugin(layer : LaneLayer,
  override def onReadHartId: UInt = apiIo.onReadHartId
  override def onReadHalt(): Unit = apiIo.onReadHalt := True
 
- override def onReadToWriteBits: Bits = ???
+ override def onReadToWriteBits: Bits = apiIo.onReadToWriteBits
 
  override def isWriting: Bool = apiIo.isWriting
  override def onWriteHalt(): Unit = apiIo.onWriteHalt := True
@@ -177,14 +177,15 @@ class CsrAccessPlugin(layer : LaneLayer,
 
  assert(!(up(LANE_SEL) && SEL && hasCancelRequest), "CsrAccessPlugin saw forbidden select && cancel request")
  val imm = IMM(UOP)
+ val csrAddress = UOP(Const.csrRange)
  val immZero = imm.z === 0
  val srcZero = CSR_IMM ? immZero otherwise UOP(Const.rs1Range) === 0
  val csrWrite = !(CSR_MASK && srcZero)
  val csrRead = !(!CSR_MASK && !rd.ENABLE)
  val sels = grouped.map(e => e._1 -> Bool().setName("COMB_CSR_" + filterToName(e._1)))
  for ((filter, sel) <- sels) sel := (filter match {
- case filter: Int => UOP(Const.csrRange) === filter
- case filter: CsrListFilter => filter.mapping.map(UOP(Const.csrRange) === _).orR
+ case filter: Int => csrAddress === filter
+ case filter: CsrListFilter => filter.mapping.map(csrAddress === _).orR
  })
  val implemented = sels.values.orR
 
@@ -222,7 +223,7 @@ class CsrAccessPlugin(layer : LaneLayer,
  apiIo.onDecodeRead := csrRead
  apiIo.onDecodeWrite := csrWrite
  apiIo.onDecodeHartId := Global.HART_ID
- apiIo.onDecodeAddress := UOP(Const.csrRange).asUInt
+ apiIo.onDecodeAddress := csrAddress.asUInt
 
  val iLogic = integrated generate new Area{
  connectRegs()

diff --git a/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala b/src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala
@@ -6,11 +6,11 @@ import spinal.lib._
 import spinal.lib.fsm._
 import spinal.lib.misc.plugin.FiberPlugin
 import vexiiriscv.Global._
-import vexiiriscv.execute.{CsrAccessPlugin, CsrRamPlugin, CsrRamService, ExecuteLanePlugin}
+import vexiiriscv.execute.{CsrAccessPlugin, CsrListFilter, CsrRamPlugin, CsrRamService, ExecuteLanePlugin}
 import vexiiriscv.riscv._
 import vexiiriscv.riscv.Riscv._
 import vexiiriscv._
-import vexiiriscv.fetch.PcService
+import vexiiriscv.fetch.{Fetch, PcService}
 import vexiiriscv.schedule.Ages
 
 import scala.collection.mutable
@@ -175,6 +175,11 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int], trapAt : Int
 
  assert(HART_COUNT.get == 1)
 
+ // Implement read-only CSR space
+ when(cap.onDecodeWrite && cap.onDecodeAddress(11 downto 10) === U"11") {
+ cap.onDecodeTrap()
+ }
+
  val csrs = for(hartId <- 0 until HART_COUNT) yield new Area{
  val hartIo = io.harts(hartId)
  val api = cap.hart(hartId)
@@ -254,22 +259,23 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int], trapAt : Int
  val tval = crs.readWriteRam(CSR.MTVAL)
  val epc = crs.readWriteRam(CSR.MEPC)
  val scratch = crs.readWriteRam(CSR.MSCRATCH)
-// for(i <- 0 until 16) cap.readWriteRam(CSR.MHPMCOUNTER3+i)
-
-
-// for (i <- 0 until 4) cap.readWrite(CSR.MHPMCOUNTER3+i, 0 -> Reg(Bits(32 bits)).init(0))
-
 
  hartIo.spec.addInterrupt(ip.mtip && ie.mtie, id = 7, privilege = 3, delegators = Nil)
  hartIo.spec.addInterrupt(ip.msip && ie.msie, id = 3, privilege = 3, delegators = Nil)
  hartIo.spec.addInterrupt(ip.meip && ie.meie, id = 11, privilege = 3, delegators = Nil)
  }
  }
 
+ val tvecFilter = CsrListFilter(List(CSR.MTVEC) ++ p.withSupervisor.option(CSR.STVEC))
+ val epcFilter = CsrListFilter(List(CSR.MEPC) ++ p.withSupervisor.option(CSR.SEPC))
+ cap.onWrite(tvecFilter, false) {cap.onWriteBits(0, 2 bits) := 0}
+ cap.onWrite(epcFilter, false) {cap.onWriteBits(0, log2Up(Fetch.SLICE_BYTES) bits) := 0}
+
 
  ramRetainers.csr.release()
 
  trapLock.await()
+
  val harts = for(hartId <- 0 until HART_COUNT) yield new Area{
  val hartIo = io.harts(hartId)
  val csr = csrs(hartId)