Some refractoring

src/main/scala/vexiiriscv/execute/BarrelShifterPlugin.scala

@@ -53,7 +53,7 @@ class BarrelShifterPlugin(val layer : LaneLayer,
 
  uopRetainer.release()
 
- val shift = new eu.Execute(shiftAt) {
+ val shift = new el.Execute(shiftAt) {
  val ss = SrcStageables
  val amplitude = srcp.SRC2(log2Up(Riscv.XLEN.get) - 1 downto 0).asUInt
  val reversed = Mux[SInt](LEFT, srcp.SRC1.reversed, srcp.SRC1)
@@ -72,7 +72,7 @@ class BarrelShifterPlugin(val layer : LaneLayer,
  SHIFT_RESULT := B(patched)
  }
 
- val format = new eu.Execute(formatAt) {
+ val format = new el.Execute(formatAt) {
  wb.valid := SEL
  wb.payload := SHIFT_RESULT
  }

src/main/scala/vexiiriscv/execute/BranchPlugin.scala

@@ -80,7 +80,7 @@ class BranchPlugin(val layer : LaneLayer,
  spec.mayFlushUpTo(jumpAt)
  }
 
- val age = eu.getExecuteAge(jumpAt)
+ val age = el.getExecuteAge(jumpAt)
  val pcPort = pcp.newJumpInterface(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, aggregationPriority = 0)
  val historyPort = hp.map(_.newPort(age, Execute.LANE_AGE_WIDTH))
  val flushPort = sp.newFlushPort(age, laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
@@ -93,7 +93,7 @@ class BranchPlugin(val layer : LaneLayer,
  // leading to a simpler design.
  val withBtb = host.get[FetchWordPrediction].nonEmpty
 
- val alu = new eu.Execute(aluAt) {
+ val alu = new el.Execute(aluAt) {
  val ss = SrcStageables
  val EQ = insert(srcp.SRC1 === srcp.SRC2)
 
@@ -137,7 +137,7 @@ class BranchPlugin(val layer : LaneLayer,
  }
  }
 
- val jumpLogic = new eu.Execute(jumpAt) {
+ val jumpLogic = new el.Execute(jumpAt) {
  val wrongCond = withBtb.mux[Bool](Prediction.ALIGNED_JUMPED =/= alu.COND , alu.COND )
  val needFix = withBtb.mux[Bool](wrongCond || alu.COND && alu.btb.BAD_TARGET, wrongCond)
  val doIt = isValid && SEL && needFix
@@ -235,7 +235,7 @@ class BranchPlugin(val layer : LaneLayer,
 
  }
 
- val wbLogic = new eu.Execute(wbAt){
+ val wbLogic = new el.Execute(wbAt){
  wb.valid := SEL && Decode.rfaKeys.get(RD).ENABLE
  wb.payload := alu.PC_FALSE.asBits.resized //PC RESIZED
  }

src/main/scala/vexiiriscv/execute/DivPlugin.scala

@@ -50,7 +50,7 @@ class DivPlugin(val layer : LaneLayer,
 
  uopRetainer.release()
 
- val processing = new eu.Execute(divAt) {
+ val processing = new el.Execute(divAt) {
  val div = DivRadix4(width = XLEN.get)
 
  DIV_REVERT_RESULT := (RS1_REVERT ^ (RS2_REVERT && !REM)) && !(RS2_FORMATED === 0 && RS2_SIGNED && !REM) //RS2_SIGNED == RS1_SIGNED anyway
@@ -64,15 +64,15 @@ class DivPlugin(val layer : LaneLayer,
 
  val unscheduleRequest = RegNext(hasCancelRequest) clearWhen (isReady) init (False)
  val freeze = isValid && SEL && !div.io.rsp.valid & !unscheduleRequest
- eu.freezeWhen(freeze)
+ el.freezeWhen(freeze)
 
  val selected = REM ? div.io.rsp.remain otherwise div.io.rsp.result
 
  def twoComplement(that: Bits, enable: Bool): UInt = (Mux(enable, ~that, that).asUInt + enable.asUInt)
  DIV_RESULT := twoComplement(B(selected), DIV_REVERT_RESULT).asBits.resized
  }
 
- val writeback = new eu.Execute(writebackAt){
+ val writeback = new el.Execute(writebackAt){
  formatBus.valid := SEL
  formatBus.payload := DIV_RESULT
  }

src/main/scala/vexiiriscv/execute/EnvPlugin.scala

@@ -29,7 +29,7 @@ class EnvPlugin(layer : LaneLayer,
  val ioRetainer = retains(sp.elaborationLock, ts.trapLock)
  awaitBuild()
 
- val age = eu.getExecuteAge(executeAt)
+ val age = el.getExecuteAge(executeAt)
  val trapPort = ts.newTrap(age, Execute.LANE_AGE_WIDTH)
  val flushPort = sp.newFlushPort(age, Execute.LANE_AGE_WIDTH, true)
 
@@ -51,7 +51,7 @@ class EnvPlugin(layer : LaneLayer,
  uopRetainer.release()
  ioRetainer.release()
 
- val exe = new eu.Execute(executeAt){
+ val exe = new el.Execute(executeAt){
  flushPort.valid := False
  flushPort.hartId := Global.HART_ID
  flushPort.uopId := Decode.UOP_ID

src/main/scala/vexiiriscv/execute/ExecutionUnitElementSimple.scala

@@ -66,13 +66,13 @@ abstract class ExecutionUnitElementSimple(layer : LaneLayer) extends FiberPlugin
  val SEL = Payload(Bool())
 
  class Logic extends ExecuteUnitElementSimple.Api(layer, host.find[SrcPlugin](_.layer == layer), SEL, rsUnsignedPlugin = host.get[RsUnsignedPlugin].getOrElse(null)) with Area with PostInitCallback {
- val eu = layer.el
+ val el = layer.el
  val srcp = srcPlugin
  val ifp = host.find[IntFormatPlugin](_.laneName == layer.el.laneName)
- val uopRetainer = retains(eu.uopLock, srcp.elaborationLock, ifp.elaborationLock)
- val euPipelineRetainer = retains(eu.pipelineLock)
+ val uopRetainer = retains(el.uopLock, srcp.elaborationLock, ifp.elaborationLock)
+ val euPipelineRetainer = retains(el.pipelineLock)
 
- eu.setDecodingDefault(SEL, False)
+ el.setDecodingDefault(SEL, False)
 
  override def postInitCallback() = {
  euPipelineRetainer.release()

src/main/scala/vexiiriscv/execute/IntAluPlugin.scala

@@ -68,7 +68,7 @@ class IntAluPlugin(var layer: LaneLayer,
 
  uopRetainer.release()
 
- val alu = new eu.Execute(aluAt) {
+ val alu = new el.Execute(aluAt) {
  val ss = SrcStageables
 
  val bitwise = ALU_BITWISE_CTRL.mux(
@@ -86,7 +86,7 @@ class IntAluPlugin(var layer: LaneLayer,
  ALU_RESULT := result.asBits
  }
 
- val format = new eu.Execute(formatAt) {
+ val format = new el.Execute(formatAt) {
  wb.valid := SEL
  wb.payload := ALU_RESULT
  }

src/main/scala/vexiiriscv/execute/MulPlugin.scala

@@ -36,7 +36,7 @@ class MulPlugin(val layer : LaneLayer,
 
  if (bufferedHigh == None) bufferedHigh = Some(Riscv.XLEN >= 64)
  if (bufferedHigh.get) {
- eu.setDecodingDefault(HIGH, False)
+ el.setDecodingDefault(HIGH, False)
  }
 
  val formatBus = newWriteback(ifp, writebackAt)
@@ -73,9 +73,9 @@ class MulPlugin(val layer : LaneLayer,
  }
  import keys._
 
- val src = new eu.Execute(srcAt) {
- val rs1 = up(eu(IntRegFile, RS1))
- val rs2 = up(eu(IntRegFile, RS2))
+ val src = new el.Execute(srcAt) {
+ val rs1 = up(el(IntRegFile, RS1))
+ val rs2 = up(el(IntRegFile, RS2))
  useRsUnsignedPlugin match {
  case false => {
  MUL_SRC1 := (RS1_SIGNED && rs1.msb) ## (rs1)
@@ -92,7 +92,7 @@ class MulPlugin(val layer : LaneLayer,
  }
 
  // Generate all the partial multiplications
- val mul = new eu.Execute(mulAt) {
+ val mul = new el.Execute(mulAt) {
  // MulSpliter.splits Will generate a data model of all partial multiplications
  val splits = MulSpliter(SRC_WIDTH, SRC_WIDTH, splitWidthA, splitWidthB, !useRsUnsignedPlugin, !useRsUnsignedPlugin)
  // Generate the partial multiplications from the splits data model
@@ -114,7 +114,7 @@ class MulPlugin(val layer : LaneLayer,
  var ptr = 0
  }
 
- val steps = for(stepId <- sumsSpec.indices) yield new eu.Execute(sumAt + stepId) {
+ val steps = for(stepId <- sumsSpec.indices) yield new el.Execute(sumAt + stepId) {
  val (stepWidth, stepLanes) = sumsSpec(stepId)
  // Generate the specification for ever adders of the current step
  val addersSpec = AdderAggregator(
@@ -147,7 +147,7 @@ class MulPlugin(val layer : LaneLayer,
  }
  }
 
- val writeback = new eu.Execute(writebackAt) {
+ val writeback = new el.Execute(writebackAt) {
  assert(sourcesSpec.size == 1)
  val result = useRsUnsignedPlugin match {
  case false => apply(sourceToSignal(sourcesSpec.head))
@@ -157,7 +157,7 @@ class MulPlugin(val layer : LaneLayer,
  val buffer = bufferedHigh.get generate new Area{
  val valid = RegNext(False) init (False) setWhen (isValid && !isReady && !hasCancelRequest)
  val data = RegNext(result(XLEN, XLEN bits))
- eu.freezeWhen(isValid && HIGH && !valid)
+ el.freezeWhen(isValid && HIGH && !valid)
  }
 
  formatBus.valid := SEL

src/main/scala/vexiiriscv/execute/SimdAddPlugin.scala

@@ -59,10 +59,10 @@ class SimdAddPlugin(val layer : LaneLayer) extends ExecutionUnitElementSimple(la
  uopRetainer.release()
 
  //Let's define some logic in the execute lane [0]
- val process = new eu.Execute(id = 0) {
+ val process = new el.Execute(id = 0) {
  //Get the RISC-V RS1/RS2 values from the register file
- val rs1 = eu(IntRegFile, RS1).asUInt
- val rs2 = eu(IntRegFile, RS2).asUInt
+ val rs1 = el(IntRegFile, RS1).asUInt
+ val rs2 = el(IntRegFile, RS2).asUInt
 
  //Do some computation
  val rd = UInt(32 bits)