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Got Data l1 to generate hardware
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@Dolu1990
Dolu1990 committed Jan 24, 2024
1 parent e1ad8b5 commit 3dd313a
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Showing 3 changed files with 118 additions and 77 deletions.
30 changes: 27 additions & 3 deletions src/main/scala/vexiiriscv/Param.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -62,8 +62,8 @@ class ParamSimple(){
performanceCounters = 4
privParam.withSupervisor = true
privParam.withUser = true
withMmu = true
withRva = true
withMmu = false
withRva = false
withRvc = false
withAlignerBuffer = withRvc
withFetchL1 = false
Expand Down Expand Up @@ -320,7 +320,31 @@ class ParamSimple(){
if(withLsuL1){
plugins += new LsuPlugin(
layer = early0,
withRva = withRva
withRva = withRva,
translationStorageParameter = MmuStorageParameter(
levels = List(
MmuStorageLevel(
id = 0,
ways = 4,
depth = 32
),
MmuStorageLevel(
id = 1,
ways = 2,
depth = 32
)
),
priority = 1
),
translationPortParameter = withMmu match {
case false => null
case true => MmuPortParameter(
readAt = 0,
hitsAt = 1,
ctrlAt = 1,
rspAt = 1
)
}
)
plugins += new LsuL1Plugin(
lane = lane0,
Expand Down
53 changes: 31 additions & 22 deletions src/main/scala/vexiiriscv/execute/lsu/LsuL1Plugin.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,14 +14,13 @@ object LsuL1 extends AreaObject{
val SEL = Payload(Bool())
val LOAD, AMO, SC, LR = Payload(Bool())
val MIXED_ADDRESS = Payload(Global.MIXED_ADDRESS)
val VIRTUAL_ENABLE = Payload(Bool())
val PHYSICAL_ADDRESS = Payload(Global.PHYSICAL_ADDRESS)
val WRITE_DATA = Payload(Bits(Riscv.LSLEN bits))
val WRITE_MASK = Payload(Bits(Riscv.LSLEN/8 bits))

// L1 ->
val PHYSICAL_ADDRESS = Payload(Global.PHYSICAL_ADDRESS)
val READ_DATA = Payload(Bits(Riscv.LSLEN bits))
val REDO, MISS, ACCESS_FAULT, PAGE_FAULT = Payload(Bool())
val REDO, MISS, FAULT = Payload(Bool())
}

class LsuL1Plugin(val lane : ExecuteLaneService,
Expand Down Expand Up @@ -96,8 +95,6 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val bus = master(LsuL1Bus(memParameter))

val ABORD = Payload(Bool())
val CPU_WORD = Payload(Bits(cpuWordWidth bits))
val CPU_MASK = Payload(Bits(cpuWordWidth / 8 bits))
val WAYS_HAZARD = Payload(Bits(wayCount bits))
val REDO_ON_DATA_HAZARD = Payload(Bool())
val BANK_BUSY = Payload(Bits(bankCount bits))
Expand All @@ -122,9 +119,6 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val WAYS_TAGS = Payload(Vec.fill(wayCount)(Tag()))
val WAYS_HITS = Payload(Bits(wayCount bits))
val WAYS_HIT = Payload(Bool())
val MISS = Payload(Bool())
val FAULT = Payload(Bool())
val REDO = Payload(Bool())
val IO = Payload(Bool())
val REFILL_SLOT = Payload(Bits(refillCount bits))
val REFILL_SLOT_FULL = Payload(Bool())
Expand All @@ -141,7 +135,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val BANKS_MUXES = Payload(Vec.fill(bankCount)(Bits(cpuWordWidth bits)))

val tagsWriteArbiter = new Reservation()
val bankWriteArbiter = new Reservation()
val bankWriteArbiter = new Reservation() //TODO
val bankReadArbiter = new Reservation()

val refillCompletions = Bits(refillCount bits)
Expand Down Expand Up @@ -172,7 +166,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val mem = Mem.fill(linePerWay)(Tag())
mem.write(waysWrite.address, waysWrite.tag, waysWrite.mask(id))
val lsuRead = new Area {
val cmd = Flow(mem.addressType).setIdle()
val cmd = Flow(mem.addressType)
val rsp = if (tagsReadAsync) mem.readAsync(cmd.payload) else mem.readSync(cmd.payload, cmd.valid)
KeepAttribute(rsp) //Ensure that it will not use 2 cycle latency ram block
}
Expand All @@ -189,6 +183,7 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
}
}

//TODO ensure that no invalidate happen when there is anything happening anywere else
val invalidate = new Area {
val counter = Reg(UInt(log2Up(linePerWay) + 1 bits)) init (0)
val done = counter.msb
Expand All @@ -203,11 +198,9 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
}

val firstEver = RegInit(True) clearWhen (done)
when(!done && firstEver) {
plru.write.valid := True
plru.write.address := counter.resized
plru.write.data.clearAll()
}
plru.write.valid := !done && firstEver
plru.write.address := counter.resized
plru.write.data.clearAll()
}

class PriorityArea(slots: Seq[(Bool, Bits)]) extends Area {
Expand Down Expand Up @@ -321,7 +314,12 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val rspWithData = withCoherency.mux(bus.read.rsp.withData, True)
if (withCoherency) assert(!(bus.read.rsp.valid && !rspWithData && slots.map(_.data).read(bus.read.rsp.id)), "Data cache asked for data but didn't recieved any :(")

val bankWriteNotif = B(0, bankCount bits)
val bankWriteNotif = Bits(bankCount bits)
val writeReservation = bankWriteArbiter.create(0)
when(bus.read.rsp.valid) {
writeReservation.takeIt()
assert(writeReservation.win)
}
for ((bank, bankId) <- banks.zipWithIndex) {
if (!reducedBankWidth) {
bankWriteNotif(bankId) := bus.read.rsp.valid && rspWithData && way === bankId
Expand Down Expand Up @@ -658,13 +656,13 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
}

val bankMuxStd = !reducedBankWidth generate new lane.Execute(bankMuxAt){
CPU_WORD := OhMux.or(WAYS_HITS, BANKS_MUXES)
READ_DATA := OhMux.or(WAYS_HITS, BANKS_MUXES)
}

val bankMuxReduced = reducedBankWidth generate new lane.Execute(bankMuxAt){
val wayId = OHToUInt(WAYS_HITS)
val bankId = (wayId >> log2Up(bankCount / memToBankRatio)) @@ ((wayId + (MIXED_ADDRESS(log2Up(bankWidth / 8), log2Up(bankCount) bits))).resize(log2Up(bankCount / memToBankRatio)))
CPU_WORD := BANKS_MUXES.read(bankId) //MuxOH(WAYS_HITS, BANKS_MUXES)
READ_DATA := BANKS_MUXES.read(bankId) //MuxOH(WAYS_HITS, BANKS_MUXES)
}


Expand Down Expand Up @@ -706,6 +704,13 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
WAYS_HIT := B(WAYS_HITS).orR
}

val preCtrl = new lane.Execute(ctrlAt){
NEED_UNIQUE := !LOAD || LR
ABORD := False //TODO
WAYS_HAZARD := 0 //TODO
LOCKED := False //TODO
}

// val rcl = new lane.Execute(ctrlAt){
// REFILL_HITS := B(refill.slots.map(r => r.valid && r.address(hazardCheckRange) === PHYSICAL_ADDRESS(hazardCheckRange)))
// }
Expand All @@ -715,10 +720,10 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
val core = new Plru(wayCount, false)
core.io.context.state := PLRU
core.io.update.id.assignDontCare()

plru.write.valid := False
plru.write.address := MIXED_ADDRESS(lineRange)
plru.write.data := core.io.update.state
when(SEL) {
plru.write.address := MIXED_ADDRESS(lineRange)
plru.write.data := core.io.update.state
}
}

val reservation = tagsWriteArbiter.create(2)
Expand Down Expand Up @@ -801,5 +806,9 @@ class LsuL1Plugin(val lane : ExecuteLaneService,
// REFILL_SLOT := REFILL_HITS.andMask(!refillLoaded) | refill.free.andMask(askRefill)
}
}

tagsWriteArbiter.build()
bankWriteArbiter.build()
bankReadArbiter.build()
}
}
112 changes: 60 additions & 52 deletions src/main/scala/vexiiriscv/execute/lsu/LsuPlugin.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,31 +16,30 @@ import vexiiriscv.{Global, riscv}

class LsuPlugin(var layer : LaneLayer,
var withRva : Boolean,
// var translationStorageParameter: Any,
// var translationPortParameter: Any,
var translationStorageParameter: Any,
var translationPortParameter: Any,
var addressAt: Int = 0,
var ctrlAt: Int = 2,
var wbAt : Int = 2) extends FiberPlugin with DBusAccessService{

val WITH_L1 = Payload(Bool())
override def accessRefillCount: Int = 0
override def accessWake: Bits = B(0)

val logic = during setup new Area{
val elp = host.find[ExecuteLanePlugin](_.laneName == layer.laneName)
val ifp = host.find[IntFormatPlugin](_.laneName == layer.laneName)
val srcp = host.find[SrcPlugin](_.layer == layer)
// val ats = host[AddressTranslationService]
val ats = host[AddressTranslationService]
val ts = host[TrapService]
val ss = host[ScheduleService]
val buildBefore = retains(elp.pipelineLock/*, ats.portsLock*/)
// val atsStorageLock = retains(ats.storageLock)
val buildBefore = retains(elp.pipelineLock, ats.portsLock)
val atsStorageLock = retains(ats.storageLock)
val retainer = retains(elp.uopLock, srcp.elaborationLock, ifp.elaborationLock, ts.trapLock, ss.elaborationLock)
awaitBuild()
Riscv.RVA.set(withRva)

// val translationStorage = ats.newStorage(translationStorageParameter)
// atsStorageLock.release()
val translationStorage = ats.newStorage(translationStorageParameter)
atsStorageLock.release()

val trapPort = ts.newTrap(layer.el.getAge(ctrlAt), Execute.LANE_AGE_WIDTH)
val flushPort = ss.newFlushPort(layer.el.getExecuteAge(addressAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
Expand Down Expand Up @@ -80,54 +79,57 @@ class LsuPlugin(var layer : LaneLayer,
SIZE := Decode.UOP(13 downto 12).asUInt
}

val busParam = LsuCachelessBusParam(
addressWidth = Global.PHYSICAL_WIDTH,
dataWidth = Riscv.LSLEN,
hartIdWidth = Global.HART_ID_WIDTH,
uopIdWidth = Decode.UOP_ID_WIDTH,
withAmo = withRva
)
val bus = master(LsuCachelessBus(busParam))
// val busParam = LsuCachelessBusParam(
// addressWidth = Global.PHYSICAL_WIDTH,
// dataWidth = Riscv.LSLEN,
// hartIdWidth = Global.HART_ID_WIDTH,
// uopIdWidth = Decode.UOP_ID_WIDTH,
// withAmo = withRva
// )
// val bus = master(LsuCachelessBus(busParam))

accessRetainer.await()

// val onAddress = new addressCtrl.Area{
// val RAW_ADDRESS = insert(srcp.ADD_SUB.asUInt)
//
// val translationPort = ats.newTranslationPort(
// nodes = Seq(forkCtrl.down),
// rawAddress = RAW_ADDRESS,
// allowRefill = insert(True),
// usage = AddressTranslationPortUsage.LOAD_STORE,
// portSpec = translationPortParameter,
// storageSpec = translationStorage
// )
// }

val l1 = LsuL1
val onAddress = new elp.Execute(addressAt){
// val tpk = onAddress.translationPort.keys

val onAddress0 = new elp.Execute(addressAt){
val translationPort = ats.newTranslationPort(
nodes = Seq(elp.execute(addressAt).down, elp.execute(addressAt+1).down),
rawAddress = l1.MIXED_ADDRESS,
allowRefill = insert(True),
usage = AddressTranslationPortUsage.LOAD_STORE,
portSpec = translationPortParameter,
storageSpec = translationStorage
)
val RS2 = elp(IntRegFile, riscv.RS2)
val mapping = (0 to log2Up(Riscv.LSLEN / 8)).map { size =>
val w = (1 << size) * 8
size -> up(RS2)(0, w bits).#*(Riscv.LSLEN / w)
}

val SEL = Payload(Bool())
l1.SEL := isValid && SEL //TODO inibate SEL on cancel / throw
l1.MIXED_ADDRESS := srcp.ADD_SUB.asUInt
l1.VIRTUAL_ENABLE := True
l1.WRITE_MASK := AddressToMask(l1.MIXED_ADDRESS, SIZE, Riscv.LSLEN/8)
l1.WRITE_DATA := bus.cmd.size.muxListDc(mapping)

val MISS_ALIGNED = insert((1 to log2Up(LSLEN / 8)).map(i => SIZE === i && l1.MIXED_ADDRESS(i - 1 downto 0) =/= 0).orR)
l1.WRITE_MASK := AddressToMask(l1.MIXED_ADDRESS, SIZE, Riscv.LSLEN / 8)
l1.WRITE_DATA := SIZE.muxListDc(mapping)
l1.LOAD := LOAD
l1.AMO := AMO
l1.SC := SC
l1.LR := LR
}

val tpk = onAddress0.translationPort.keys



for(eid <- addressAt + 1 to ctrlAt) elp.execute(eid).up(WITH_L1).setAsReg().init(False)
val onAddress1 = new elp.Execute(addressAt+1) {
l1.PHYSICAL_ADDRESS := tpk.TRANSLATED
}


for(eid <- addressAt + 1 to ctrlAt) elp.execute(eid).up(l1.SEL).setAsReg().init(False)

val onCtrl = new elp.Execute(ctrlAt) {
val MISS_ALIGNED = insert((1 to log2Up(LSLEN / 8)).map(i => SIZE === i && l1.MIXED_ADDRESS(i - 1 downto 0) =/= 0).orR)

flushPort.valid := False
flushPort.hartId := Global.HART_ID
flushPort.uopId := Decode.UOP_ID
Expand All @@ -145,39 +147,45 @@ class LsuPlugin(var layer : LaneLayer,

val skip = False

// if (withSpeculativeLoadFlush) when(LOAD && tpk.IO && elp.atRiskOfFlush(forkAt)) {
// skip := True
// trapPort.exception := False
// trapPort.code := TrapReason.REDO
// }
when(l1.FAULT) {
skip := True
trapPort.exception := True
trapPort.code := CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT
trapPort.code(1) setWhen (!LOAD)
}

when(l1.REDO) {
skip := True
trapPort.exception := False
trapPort.code := TrapReason.REDO
}

when(l1.PAGE_FAULT/* || LOAD.mux(!tpk.ALLOW_READ, !tpk.ALLOW_WRITE)*/) {
when(tpk.PAGE_FAULT || LOAD.mux(!tpk.ALLOW_READ, !tpk.ALLOW_WRITE)) {
skip := True
trapPort.exception := True
trapPort.code := CSR.MCAUSE_ENUM.LOAD_PAGE_FAULT
trapPort.code(1) setWhen (!LOAD)
}

when(l1.ACCESS_FAULT) {
when(tpk.ACCESS_FAULT) {
skip := True
trapPort.exception := True
trapPort.code := CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT
trapPort.code(1) setWhen (!LOAD)
}

// trapPort.arg(0, 2 bits) := LOAD.mux(B(TrapArg.LOAD, 2 bits), B(TrapArg.STORE, 2 bits))
// trapPort.arg(2, l1.getStorageIdWidth() bits) := l1.getStorageId()
when(l1.REDO) {
???
trapPort.arg(0, 2 bits) := LOAD.mux(B(TrapArg.LOAD, 2 bits), B(TrapArg.STORE, 2 bits))
trapPort.arg(2, ats.getStorageIdWidth() bits) := ats.getStorageId(translationStorage)
when(tpk.REDO) {
skip := True
trapPort.exception := False
trapPort.code := TrapReason.MMU_REFILL
}

when(onAddress.MISS_ALIGNED) {
when(MISS_ALIGNED) {
skip := True
trapPort.exception := True
trapPort.code := LOAD.mux[Bits](CSR.MCAUSE_ENUM.LOAD_MISALIGNED, CSR.MCAUSE_ENUM.STORE_MISALIGNED).andMask(onAddress.MISS_ALIGNED).resized
trapPort.code := LOAD.mux[Bits](CSR.MCAUSE_ENUM.LOAD_MISALIGNED, CSR.MCAUSE_ENUM.STORE_MISALIGNED).andMask(MISS_ALIGNED).resized
}

when(isValid && SEL && skip) {
Expand Down

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