fix some 64 bits width issues

SpinalHDL · Jan 12, 2024 · 4ca86f3 · 4ca86f3
1 parent 628bb32
commit 4ca86f3
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Showing 7 changed files with 15 additions and 14 deletions.
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
diff --git a/src/main/scala/vexiiriscv/execute/BranchPlugin.scala b/src/main/scala/vexiiriscv/execute/BranchPlugin.scala
@@ -238,7 +238,7 @@ class BranchPlugin(val layer : LaneLayer,
 
  val wbLogic = new el.Execute(wbAt){
  wb.valid := SEL && Decode.rfaKeys.get(RD).ENABLE
- wb.payload := alu.PC_FALSE.asBits.resized //PC RESIZED
+ wb.payload := S(alu.PC_FALSE, Riscv.XLEN bits).asBits
  }
  }
 }
diff --git a/src/main/scala/vexiiriscv/riscv/Rvi.scala b/src/main/scala/vexiiriscv/riscv/Rvi.scala
@@ -153,7 +153,7 @@ object Rvi extends AreaObject {
  loadSpec(LRW) = LoadSpec(32, true)
  loadSpec(SCW) = LoadSpec(8, true) //8 bits to allow sc to only write the 8 lsb (less logic)
 
- loadSpec(LRD) = LoadSpec(32, true)
+ loadSpec(LRD) = LoadSpec(64, true)
  loadSpec(SCD) = LoadSpec(8, true)
 
  loadSpec(AMOSWAPW) = LoadSpec(32, true)

diff --git a/src/main/scala/vexiiriscv/test/VexiiRiscvProbe.scala b/src/main/scala/vexiiriscv/test/VexiiRiscvProbe.scala
@@ -3,6 +3,7 @@ package vexiiriscv.test
 import rvls.spinal.{TraceBackend, TraceIo}
 import spinal.core._
 import spinal.core.sim._
+import vexiiriscv.Global.PC_WIDTH
 import vexiiriscv._
 import vexiiriscv.decode.Decode
 import vexiiriscv.execute.LsuCachelessPlugin
@@ -134,7 +135,7 @@ class VexiiRiscvProbe(cpu : VexiiRiscv, kb : Option[konata.Backend], withRvls :
  case None => "M"
  }
  tracer.newCpuMemoryView(hartId, 16, 16) //TODO readIds writeIds
- tracer.newCpu(hartId, s"RV${xlen}IMA", csrp, 32, hartId)
+ tracer.newCpu(hartId, s"RV${xlen}IMA", csrp, cpu.database(PC_WIDTH), hartId)
  val pc = pcExtends(0x80000000l)
  tracer.setPc(hartId, pc)
  this
@@ -300,7 +301,7 @@ class VexiiRiscvProbe(cpu : VexiiRiscv, kb : Option[konata.Backend], withRvls :
  val ctx = hart.decode(decodeId)
  if(spawn){
  val fetchId = decode.fetchId.toInt
- ctx.pc = pcExtends(decode.pc.toLong)
+ ctx.pc = decode.pc.toLong
  ctx.fetchId = fetchId
  ctx.spawnAt = cycle
  ctx.fireAt = -1

diff --git a/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala b/src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala
@@ -42,7 +42,7 @@ class WhiteboxerPlugin extends FiberPlugin{
  val fire = wrap(c.up.isFiring)
  val spawn = wrap(c.up.transactionSpawn)
  val hartId = wrap(c(Global.HART_ID))
- val pc = wrap(c(Global.PC))
+ val pc = wrap(c(Global.PC).asSInt.resize(64 bits))
  val fetchId = wrap(c(Fetch.ID))
  val decodeId = wrap(c(Decode.DOP_ID))
  }

diff --git a/src/test/scala/vexiiriscv/scratchpad/Play.scala b/src/test/scala/vexiiriscv/scratchpad/Play.scala
@@ -22,9 +22,9 @@ object Play1 extends App {
 // host[LsuCachelessPlugin].logic.redoPort,
 // src.logic.src(src.SRC1)
 // ))
- println(PathTracer.impl(
- host[LsuCachelessPlugin].logic.redoPort,
- src.logic.src(src.SRC1)
- ).report())
+// println(PathTracer.impl(
+// host[LsuCachelessPlugin].logic.redoPort,
+// src.logic.src(src.SRC1)
+// ).report())
 }
 
diff --git a/src/test/scala/vexiiriscv/tester/Regression.scala b/src/test/scala/vexiiriscv/tester/Regression.scala
@@ -143,9 +143,9 @@ class RegressionSingle(compiled : SimCompiled[VexiiRiscv], dutArgs : Seq[String]
  }
 
  val freertos = List(
- "blocktim", "countsem", "EventGroupsDemo", "flop", "integer", "QPeek",
+ "sp_flop", "integer", "blocktim", "countsem", "EventGroupsDemo", "flop", "QPeek",
  "QueueSet", "recmutex", "semtest", "TaskNotify", "dynamic",
- "GenQTest", "PollQ", "QueueOverwrite", "QueueSetPolling", "sp_flop", "test1"
+ "GenQTest", "PollQ", "QueueOverwrite", "QueueSetPolling", "test1"
  )
  for(name <- freertos.take(4)){
  val args = newArgs()
@@ -193,7 +193,7 @@ class RegressionSingle(compiled : SimCompiled[VexiiRiscv], dutArgs : Seq[String]
  val tp = new File(compiled.simConfig.getTestPath(""))
  FileUtils.forceMkdir(tp)
  val argsFile = new BufferedWriter(new FileWriter(new File(tp, "args")))
- argsFile.write(dutArgs.map(v => if (v.contains(" ")) s"'$v'" else v).mkString(" "))
+ argsFile.write(dutArgs.map(v => if (v.contains(" ")) '"' + v + '"' else v).mkString(" "))
  argsFile.close()
 
  for(args <- testArgs){
@@ -213,7 +213,7 @@ class RegressionSingle(compiled : SimCompiled[VexiiRiscv], dutArgs : Seq[String]
  val job = new AsyncJob(toStdout = false, logsPath = testPath)({
  FileUtils.forceMkdir(testPath)
  val argsFile = new BufferedWriter(new FileWriter(new File(testPath, "args")))
- argsFile.write(args.args.map(v => if(v.contains(" ")) s"'$v'" else v).mkString(" "))
+ argsFile.write(args.args.map(v => if(v.contains(" ")) '"' + v + '"' else v).mkString(" "))
  argsFile.close()
 
  t.test(compiled)