Add trap arg

src/main/scala/vexiiriscv/decode/DecoderPlugin.scala

@@ -146,13 +146,14 @@ class DecoderPlugin(var decodeAt : Int) extends FiberPlugin with DecoderService
  trapPort.code := CSR.MCAUSE_ENUM.ILLEGAL_INSTRUCTION
  trapPort.laneAge := laneId
  trapPort.hartId := Global.HART_ID
+ trapPort.arg := 0
 
  when(interruptPending){
  trapPort.code := TrapReason.INTERRUPT
  }
 
  val completionPort = Flow(CompletionPayload())
- completionPort.valid := False
+ completionPort.valid := isValid && Global.TRAP && up.transactionSpawn
  completionPort.hartId := Global.HART_ID
  completionPort.uopId := Decode.UOP_ID
  completionPort.trap := True
@@ -161,9 +162,6 @@ class DecoderPlugin(var decodeAt : Int) extends FiberPlugin with DecoderService
  when(isValid && (!LEGAL || interruptPending)) {
  bypass(Global.TRAP) := True
  trapPort.valid := !up(Global.TRAP)
- when(up.transactionSpawn){
- completionPort.valid := True
- }
  }
 
  //Will also flush instructions after a fetch trap

src/main/scala/vexiiriscv/execute/BranchPlugin.scala

@@ -198,6 +198,7 @@ class BranchPlugin(val layer : LaneLayer,
  trapPort.exception := True
  trapPort.code := CSR.MCAUSE_ENUM.FETCH_MISSALIGNED
  trapPort.tval := B(alu.PC_TRUE)
+ trapPort.arg := 0
 
  when(doIt && MISSALIGNED){
  trapPort.valid := True

src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala

@@ -247,6 +247,7 @@ class CsrAccessPlugin(layer : LaneLayer,
  trapPort.exception := True
  trapPort.code := CSR.MCAUSE_ENUM.ILLEGAL_INSTRUCTION
  trapPort.tval := UOP
+ trapPort.arg := 0
 
  val flushReg = RegInit(False) setWhen(flushPort.valid) clearWhen(!elp.isFreezed())
  when(flushReg) {
@@ -272,7 +273,7 @@ class CsrAccessPlugin(layer : LaneLayer,
  trapPort.valid := True
  trapPort.exception := False
  trapPort.code := TrapReason.JUMP
- trapPort.tval := B(INSTRUCTION_SLICE_COUNT +^ 1).resized
+ trapPort.arg := B(INSTRUCTION_SLICE_COUNT +^ 1).resized
  }
  }
  }

src/main/scala/vexiiriscv/execute/EnvPlugin.scala

@@ -59,8 +59,9 @@ class EnvPlugin(layer : LaneLayer,
 
  trapPort.valid := False
  trapPort.exception := True
- trapPort.code.assignDontCare()
  trapPort.tval := B(PC).andMask(OP === EnvPluginOp.EBREAK) //That's what spike do
+ trapPort.code.assignDontCare()
+ trapPort.arg.assignDontCare()
 
  val privilege = ps.getPrivilege(HART_ID)
  val xretPriv = Decode.UOP(29 downto 28).asUInt
@@ -78,7 +79,7 @@ class EnvPlugin(layer : LaneLayer,
  commit := True
  trapPort.exception := False
  trapPort.code := TrapReason.PRIV_RET
- trapPort.tval(1 downto 0) := xretPriv.asBits
+ trapPort.arg(1 downto 0) := xretPriv.asBits
  } otherwise {
  trapPort.code := CSR.MCAUSE_ENUM.ILLEGAL_INSTRUCTION
  }

src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala

@@ -74,6 +74,9 @@ class LsuCachelessPlugin(var layer : LaneLayer,
  val retainer = retains(elp.uopLock, srcp.elaborationLock, ifp.elaborationLock, ts.trapLock, ss.elaborationLock)
  awaitBuild()
 
+ val translationStorage = ats.newStorage(translationStorageParameter)
+ atsStorageLock.release()
+
  val trapPort = ts.newTrap(layer.el.getAge(forkAt), Execute.LANE_AGE_WIDTH)
  val flushPort = ss.newFlushPort(layer.el.getExecuteAge(addressAt), laneAgeWidth = Execute.LANE_AGE_WIDTH, withUopId = true)
  val frontend = new AguFrontend(layer, host)
@@ -107,9 +110,6 @@ class LsuCachelessPlugin(var layer : LaneLayer,
 
  retainer.release()
 
- val translationStorage = ats.newStorage(translationStorageParameter)
- atsStorageLock.release()
-
  val injectCtrl = elp.ctrl(0)
  val inject = new injectCtrl.Area {
  SIZE := Decode.UOP(13 downto 12).asUInt
@@ -174,15 +174,16 @@ class LsuCachelessPlugin(var layer : LaneLayer,
  trapPort.valid := False
  trapPort.hartId := Global.HART_ID
  trapPort.laneAge := Execute.LANE_AGE
+ trapPort.tval := onAddress.RAW_ADDRESS.asBits.resized //PC RESIZED
  trapPort.exception.assignDontCare()
  trapPort.code.assignDontCare()
- trapPort.tval.assignDontCare()
+ trapPort.arg.assignDontCare()
 
  if(withSpeculativeLoadFlush) when(LOAD && tpk.IO && elp.atRiskOfFlush(forkAt)){
  skip := True
  trapPort.exception := False
  trapPort.code := TrapReason.JUMP
- trapPort.tval(0, INSTRUCTION_SLICE_COUNT_WIDTH + 1 bits) := 0
+ trapPort.arg(0, INSTRUCTION_SLICE_COUNT_WIDTH + 1 bits) := 0
  }
 
  when(tpk.PAGE_FAULT || LOAD.mux(!tpk.ALLOW_READ, !tpk.ALLOW_WRITE)) {
@@ -203,15 +204,14 @@ class LsuCachelessPlugin(var layer : LaneLayer,
  skip := True
  trapPort.exception := False
  trapPort.code := TrapReason.MMU_REFILL
- trapPort.tval(0, 2 bits) := LOAD.mux(B(TrapArg.LOAD, 2 bits), B(TrapArg.STORE, 2 bits))
- trapPort.tval(2, ats.getStorageIdWidth() bits) := ats.getStorageId(translationStorage)
+ trapPort.arg(0, 2 bits) := LOAD.mux(B(TrapArg.LOAD, 2 bits), B(TrapArg.STORE, 2 bits))
+ trapPort.arg(2, ats.getStorageIdWidth() bits) := ats.getStorageId(translationStorage)
  }
 
  when(MISS_ALIGNED){
  skip := True
  trapPort.exception := True
  trapPort.code := LOAD.mux[Bits](CSR.MCAUSE_ENUM.LOAD_MISALIGNED, CSR.MCAUSE_ENUM.STORE_MISALIGNED).andMask(MISS_ALIGNED).resized
- trapPort.tval := onAddress.RAW_ADDRESS.asBits.resized //PC RESIZED
  }
 
  when(isValid && SEL && skip){

src/main/scala/vexiiriscv/fetch/FetchCachelessPlugin.scala

@@ -143,6 +143,7 @@ class FetchCachelessPlugin(var wordWidth : Int,
  trapPort.hartId := Global.HART_ID
  trapPort.exception.assignDontCare()
  trapPort.code.assignDontCare()
+ trapPort.arg.assignDontCare()
 
  when(rsp.error){
  TRAP := True
@@ -166,8 +167,8 @@ class FetchCachelessPlugin(var wordWidth : Int,
  TRAP := True
  trapPort.exception := False
  trapPort.code := TrapReason.MMU_REFILL
- trapPort.tval(0, 2 bits) := TrapArg.FETCH
- trapPort.tval(2, ats.getStorageIdWidth() bits) := ats.getStorageId(translationStorage)
+ trapPort.arg(0, 2 bits) := TrapArg.FETCH
+ trapPort.arg(2, ats.getStorageIdWidth() bits) := ats.getStorageId(translationStorage)
  }
 
  TRAP.clearWhen(!isValid || haltIt)

src/main/scala/vexiiriscv/memory/MmuPlugin.scala

@@ -439,7 +439,7 @@ class MmuPlugin(var spec : MmuSpec,
  }
 
  refillPorts.onMask(portOhReg){port =>
- port.rsp.valid := sel
+ port.rsp.valid := True
  port.rsp.pageFault := pageFault
  port.rsp.accessFault := accessFault
  }

src/main/scala/vexiiriscv/misc/TrapPlugin.scala

@@ -25,6 +25,7 @@ case class Trap(laneAgeWidth : Int, full : Boolean) extends Bundle{
  val exception = Bool()
  val tval = TVAL()
  val code = CODE()
+ val arg = TRAP_ARG()
  val laneAge = full generate UInt(laneAgeWidth bits)
  val hartId = full generate HART_ID()
 
@@ -101,7 +102,10 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  val ramPortRetainers = withRam generate crs.portLock()
  awaitBuild()
 
- TRAP_ARG_WIDTH.set(10) //TODO
+ val trapArgWidths = ArrayBuffer[Int](2)
+ if(ats.mayNeedRedo) trapArgWidths += 2+ats.getStorageIdWidth()
+ TRAP_ARG_WIDTH.set(trapArgWidths.max)
+
  trapLock.await()
 
  val harts = for(hartId <- 0 until HART_COUNT) yield new Area{
@@ -192,7 +196,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  val pc = Reg(PC)
 
  val xret = new Area {
- val sourcePrivilege = state.tval(1 downto 0).asUInt
+ val sourcePrivilege = state.arg(1 downto 0).asUInt
  val targetPrivilege = privilegeMux(sourcePrivilege)(
  csr.m.status.mpp,
  U"0" @@ csr.s.status.spp
@@ -279,7 +283,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  if(ats.mayNeedRedo) {
  atsRefill.cmd.valid := False
  atsRefill.cmd.address := pending.state.tval.asUInt
- atsRefill.cmd.storageId := pending.state.tval(2, ats.getStorageIdWidth() bits).asUInt
+ atsRefill.cmd.storageId := pending.state.arg(2, ats.getStorageIdWidth() bits).asUInt
  }
 
  RUNNING.whenIsActive {
@@ -291,7 +295,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
 
  val jumpTarget = Reg(PC)
  jumpTarget := pending.pc + pending.state.code.mux(
- TrapReason.JUMP -> U(pending.state.tval(0, INSTRUCTION_SLICE_COUNT_WIDTH+1 bits) << Fetch.SLICE_RANGE_LOW),
+ TrapReason.JUMP -> U(pending.state.arg(0, INSTRUCTION_SLICE_COUNT_WIDTH+1 bits) << Fetch.SLICE_RANGE_LOW),
  TrapReason.MMU_REFILL -> U(0, 3 bits),
  default -> U(4)
  )
@@ -337,7 +341,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  goto(JUMP) //TODO shave one cycle
  when(atsRefill.rsp.pageFault || atsRefill.rsp.accessFault){
  pending.state.exception := True
- switch(atsRefill.rsp.pageFault ## pending.state.tval(1 downto 0)){
+ switch(atsRefill.rsp.pageFault ## pending.state.arg(1 downto 0)){
  def add(k : Int, v : Int) = is(k){pending.state.code := v}
  add(TrapArg.FETCH , CSR.MCAUSE_ENUM.INSTRUCTION_ACCESS_FAULT)
  add(TrapArg.LOAD , CSR.MCAUSE_ENUM.LOAD_ACCESS_FAULT)
@@ -418,7 +422,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  goto(RUNNING)
  }
 
- val xretPrivilege = U(pending.state.tval(1 downto 0))
+ val xretPrivilege = U(pending.state.arg(1 downto 0))
  XRET_EPC.whenIsActive{
  crsPorts.read.valid := True
  crsPorts.read.address := privilegeMux(xretPrivilege)(
@@ -436,7 +440,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
 
  csr.privilege := pending.xret.targetPrivilege
  csr.xretAwayFromMachine setWhen (pending.xret.targetPrivilege < 3)
- switch(pending.state.tval(1 downto 0)) {
+ switch(pending.state.arg(1 downto 0)) {
  is(3) {
  if(priv.p.withUser) csr.m.status.mpp := 0
  csr.m.status.mie := csr.m.status.mpie

src/main/scala/vexiiriscv/schedule/ReschedulePlugin.scala

@@ -27,7 +27,7 @@ class ReschedulePlugin extends FiberPlugin with ScheduleService {
 // newFlushPort(age, laneAgeWidth, withUopId).setCompositeName(key, "flushPort")
 // })
 // }
- override def newTrapPort(age : Int, causeWidth : Int = 4) = trapPorts.addRet(Flow(TrapCmd(age, Global.PC_WIDTH, Global.TVAL_WIDTH, causeWidth)))
+ override def newTrapPort(age : Int, causeWidth : Int = 4) = trapPorts.addRet(Flow(TrapCmd(age, Global.PC_WIDTH, Global.TVAL_WIDTH, causeWidth, Global.TRAP_ARG_WIDTH)))
  override def isFlushedAt(age: Int, hartId: UInt, laneAge : UInt): Option[Bool] = {
  elaborationLock.await()
  val filtred = flushPorts.filter(p => p.age >= age)

src/main/scala/vexiiriscv/schedule/Service.scala

@@ -25,9 +25,10 @@ case class FlushCmd(age : Int, laneAgeWidth : Int, withUopId : Boolean) extends
  val self = Bool()
 }
 
-case class TrapCmd(age : Int, pcWidth : Int, tvalWidth : Int, causeWidth : Int) extends Bundle {
+case class TrapCmd(age : Int, pcWidth : Int, tvalWidth : Int, causeWidth : Int, trapArgWidth : Int) extends Bundle {
  val cause = UInt(causeWidth bits)
  val tval = Bits(tvalWidth bits)
+ val arg = Bits(trapArgWidth bits)
  val skipCommit = Bool() //Want to skip commit for exceptions, but not for [jump, ebreak, redo]
 }