LsuCachelessBus refractoring

src/main/scala/vexiiriscv/execute/LsuCachelessBus.scala

@@ -0,0 +1,68 @@
+package vexiiriscv.execute
+
+import spinal.core._
+import spinal.lib._
+import spinal.lib.misc.plugin.FiberPlugin
+import vexiiriscv.{Global, riscv}
+import vexiiriscv.riscv.{CSR, Const, IntRegFile, MicroOp, RS1, RS2, Riscv, Rvi}
+import AguPlugin._
+import spinal.core.fiber.Retainer
+import vexiiriscv.decode.Decode
+import vexiiriscv.fetch.FetchPipelinePlugin
+import vexiiriscv.memory.{AddressTranslationPortUsage, AddressTranslationService, DBusAccessService}
+import vexiiriscv.misc.{AddressToMask, TrapArg, TrapReason, TrapService}
+import vexiiriscv.riscv.Riscv.{LSLEN, XLEN}
+import spinal.lib.misc.pipeline._
+import vexiiriscv.decode.Decode.{INSTRUCTION_SLICE_COUNT_WIDTH, UOP}
+import vexiiriscv.schedule.{ReschedulePlugin, ScheduleService}
+
+import scala.collection.mutable
+import scala.collection.mutable.ArrayBuffer
+
+object LsuCachelessBusAmo{
+ val LR = 0x02
+ val SC = 0x03
+ val AMOSWAP = 0x01
+ val AMOADD = 0x00
+ val AMOXOR = 0x04
+ val AMOAND = 0x0C
+ val AMOOR = 0x08
+ val AMOMIN = 0x10
+ val AMOMAX = 0x14
+ val AMOMINU = 0x18
+ val AMOMAXU = 0x1c
+}
+
+case class LsuCachelessBusParam(addressWidth : Int, dataWidth : Int, hartIdWidth : Int, uopIdWidth : Int, withAmo : Boolean){
+
+}
+
+case class LsuCachelessCmd(p : LsuCachelessBusParam) extends Bundle{
+ val write = Bool()
+ val address = UInt(p.addressWidth bits)
+ val data = Bits(p.dataWidth bit)
+ val size = UInt(log2Up(log2Up(p.dataWidth / 8) + 1) bits)
+ val mask = Bits(p.dataWidth / 8 bits)
+ val io = Bool() //This is for verification purposes, allowing RVLS to track stuff
+ val fromHart = Bool() //This is for verification purposes, allowing RVLS to track stuff
+ val hartId = UInt(p.hartIdWidth bits)
+ val uopId = UInt(p.uopIdWidth bits)
+ val amoEnable = p.withAmo generate Bool()
+ val amoOp = p.withAmo generate Bits(5 bits)
+}
+
+case class LsuCachelessRsp(p : LsuCachelessBusParam) extends Bundle{
+ val error = Bool()
+ val data = Bits(p.dataWidth bits)
+ val scMiss = p.withAmo generate Bool()
+}
+
+case class LsuCachelessBus(p : LsuCachelessBusParam) extends Bundle with IMasterSlave {
+ var cmd = Stream(LsuCachelessCmd(p))
+ var rsp = Flow(LsuCachelessRsp(p))
+
+ override def asMaster(): Unit = {
+ master(cmd)
+ slave(rsp)
+ }
+}

src/main/scala/vexiiriscv/execute/LsuCachelessPlugin.scala

@@ -19,54 +19,6 @@ import vexiiriscv.schedule.{ReschedulePlugin, ScheduleService}
 import scala.collection.mutable
 import scala.collection.mutable.ArrayBuffer
 
-object CachelessBusAmo{
- val LR = 0x02
- val SC = 0x03
- val AMOSWAP = 0x01
- val AMOADD = 0x00
- val AMOXOR = 0x04
- val AMOAND = 0x0C
- val AMOOR = 0x08
- val AMOMIN = 0x10
- val AMOMAX = 0x14
- val AMOMINU = 0x18
- val AMOMAXU = 0x1c
-}
-
-case class CachelessBusParam(addressWidth : Int, dataWidth : Int, hartIdWidth : Int, uopIdWidth : Int, withAmo : Boolean){
-
-}
-
-case class CachelessCmd(p : CachelessBusParam) extends Bundle{
- val write = Bool()
- val address = UInt(p.addressWidth bits)
- val data = Bits(p.dataWidth bit)
- val size = UInt(log2Up(log2Up(p.dataWidth / 8) + 1) bits)
- val mask = Bits(p.dataWidth / 8 bits)
- val io = Bool() //This is for verification purposes, allowing RVLS to track stuff
- val fromHart = Bool() //This is for verification purposes, allowing RVLS to track stuff
- val hartId = UInt(p.hartIdWidth bits)
- val uopId = UInt(p.uopIdWidth bits)
- val amoEnable = p.withAmo generate Bool()
- val amoOp = p.withAmo generate Bits(5 bits)
-}
-
-case class CachelessRsp(p : CachelessBusParam) extends Bundle{
- val error = Bool()
- val data = Bits(p.dataWidth bits)
- val scMiss = p.withAmo generate Bool()
-}
-
-case class CachelessBus(p : CachelessBusParam) extends Bundle with IMasterSlave {
- var cmd = Stream(CachelessCmd(p))
- var rsp = Flow(CachelessRsp(p))
-
- override def asMaster(): Unit = {
- master(cmd)
- slave(rsp)
- }
-}
-
 class LsuCachelessPlugin(var layer : LaneLayer,
  var withAmo : Boolean,
  var withSpeculativeLoadFlush : Boolean, //WARNING, the fork cmd may be flushed out of existance before firing
@@ -144,14 +96,14 @@ class LsuCachelessPlugin(var layer : LaneLayer,
  val joinCtrl = elp.execute(joinAt)
  val wbCtrl = elp.execute(wbAt)
 
- val busParam = CachelessBusParam(
+ val busParam = LsuCachelessBusParam(
  addressWidth = Global.PHYSICAL_WIDTH,
  dataWidth = Riscv.LSLEN,
  hartIdWidth = Global.HART_ID_WIDTH,
  uopIdWidth = Decode.UOP_ID_WIDTH,
  withAmo = withAmo
  )
- val bus = master(CachelessBus(busParam))
+ val bus = master(LsuCachelessBus(busParam))
 
  accessRetainer.await()
 

src/main/scala/vexiiriscv/tester/TestBench.scala

@@ -375,7 +375,7 @@ class TestOptions{
  error = read(bytes, cmd.address.toInt & (p.p.dataWidth / 8 - 1))
  }
  } else {
- import vexiiriscv.execute.CachelessBusAmo._
+ import vexiiriscv.execute.LsuCachelessBusAmo._
  cmd.amoOp match {
  case LR => {
  error = read(bytes, cmd.address.toInt & (p.p.dataWidth / 8 - 1))