cleaning

src/main/scala/vexiiriscv/decode/DecoderPlugin.scala

@@ -117,7 +117,7 @@ class DecoderPlugin(var decodeAt : Int) extends FiberPlugin with DecoderService
  }
 
  val interrupt = new Area {
- val async = B(host[PrivilegedPlugin].miaou.csrs.map(_.int.pending))
+ val async = B(host[PrivilegedPlugin].logic.harts.map(_.int.pending))
  //We need to buffer interrupts request to ensure we don't generate sporadic flushes while the ctrl is stuck
  val buffered = RegNextWhen(async, !decodeCtrl.link.up.valid || decodeCtrl.link.up.ready || decodeCtrl.link.up.isCanceling) init(0)
  }

src/main/scala/vexiiriscv/memory/MmuPLugin.scala

@@ -5,7 +5,7 @@
 //import spinal.lib._
 //import spinal.lib.fsm._
 //import spinal.lib.misc.plugin.FiberPlugin
-//import spinal.lib.pipeline.{Payload, Stage}
+//import spinal.lib.misc.pipeline._
 //import vexiiriscv._
 //import Global._
 //import spinal.lib.misc.pipeline.{NodeBaseApi, Payload}
@@ -104,7 +104,7 @@
 // storageSpecs.addRet(StorageSpec(p))
 // }
 //
-// override def newTranslationPort(stages: Seq[Stage],
+// override def newTranslationPort(stages: Seq[NodeBaseApi],
 // preAddress: Payload[UInt],
 // allowRefill : Payload[Bool],
 // usage : AddressTranslationPortUsage,
@@ -180,7 +180,7 @@
 // val status = new Area{
 // val mxr = RegInit(False)
 // val sum = RegInit(False)
-// val mprv = RegInit(False) clearWhen(priv.io.harts(0).xretAwayFromMachine)
+// val mprv = RegInit(False) clearWhen(priv.hart(0).xretAwayFromMachine)
 // }
 //
 // for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csr.readWrite(offset, 19 -> status.mxr, 18 -> status.sum)

src/main/scala/vexiiriscv/misc/PrivilegedPlugin.scala

@@ -50,21 +50,23 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe
  def implementUser = p.withUser
  def implementUserTrap = p.withUserTrap
 
- def getPrivilege(hartId : UInt) : UInt = miaou.csrs.map(_.privilege).read(hartId)
+ def getPrivilege(hartId : UInt) : UInt = logic.harts.map(_.privilege).read(hartId)
 
  case class Delegator(var enable: Bool, privilege: Int)
  case class InterruptSpec(var cond: Bool, id: Int, privilege: Int, delegators: List[Delegator])
  case class ExceptionSpec(id: Int, delegators: List[Delegator])
- override def getCommitMask(hartId: Int): Bits = miaou.csrs(hartId).commitMask
- override def hasInflight(hartId: Int): Bool = miaou.csrs(hartId).hasInflight
+ override def getCommitMask(hartId: Int): Bits = logic.harts(hartId).commitMask
+ override def hasInflight(hartId: Int): Bool = logic.harts(hartId).hasInflight
 
  val misaIds = mutable.LinkedHashSet[Int]()
  def addMisa(id: Char): Unit = addMisa(id - 'A')
  def addMisa(id: Int) = {
  misaIds += id
  }
 
- val miaou = during setup new Area {
+ def hart(id : Int) = logic.harts(id)
+
+ val logic = during setup new Area {
  val cap = host[CsrAccessPlugin]
  val pp = host[PipelineBuilderPlugin]
  val pcs = host[PcService]
@@ -88,7 +90,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe
  assert(HART_COUNT.get == 1)
 
  val rdtime = in UInt (64 bits)
- val csrs = for (hartId <- 0 until HART_COUNT) yield new Area {
+ val harts = for (hartId <- 0 until HART_COUNT) yield new Area {
  val xretAwayFromMachine = False
  val commitMask = Bits(host.list[ExecuteLanePlugin].size bits)
  val hasInflight = Bool()
@@ -271,7 +273,7 @@ class PrivilegedPlugin(val p : PrivilegedParam, hartIds : Seq[Int]) extends Fibe
  val defaultTrap = new Area {
  val csrPrivilege = cap.onDecodeAddress(8, 2 bits)
  val csrReadOnly = cap.onDecodeAddress(10, 2 bits) === U"11"
- when(csrReadOnly && cap.onDecodeWrite || csrPrivilege > csrs.reader(cap.onDecodeHartId)(_.privilege)) {
+ when(csrReadOnly && cap.onDecodeWrite || csrPrivilege > harts.reader(cap.onDecodeHartId)(_.privilege)) {
  cap.onDecodeTrap()
  }
  }

src/main/scala/vexiiriscv/misc/TrapPlugin.scala

@@ -89,7 +89,7 @@ class TrapPlugin(trapAt : Int) extends FiberPlugin with TrapService {
  trapLock.await()
 
  val harts = for(hartId <- 0 until HART_COUNT) yield new Area{
- val csr = priv.miaou.csrs(hartId)
+ val csr = priv.logic.harts(hartId)
 
  val crsPorts = withRam generate new Area{
  val read = crs.ramReadPort(CsrRamService.priority.TRAP)

src/main/scala/vexiiriscv/test/WhiteboxerPlugin.scala

@@ -240,7 +240,7 @@ class WhiteboxerPlugin extends FiberPlugin{
  class InterruptsProxy {
  val priv = host[PrivilegedPlugin]
  val checkers = ArrayBuffer[InterruptChecker]()
- for ((hart, hartId) <- priv.miaou.csrs.zipWithIndex) {
+ for ((hart, hartId) <- priv.logic.harts.zipWithIndex) {
  checkers += new InterruptChecker(hartId, hart.int.m.timer, 7)
  checkers += new InterruptChecker(hartId, hart.int.m.software, 3)
  checkers += new InterruptChecker(hartId, hart.int.m.external, 11)

src/main/scala/vexiiriscv/tester/TestBench.scala

@@ -169,7 +169,7 @@ class TestOptions{
  }
  }
 
- val priv = dut.host[PrivilegedPlugin].miaou.csrs(0)
+ val priv = dut.host[PrivilegedPlugin].logic.harts(0)
  val peripheral = new PeripheralEmulator(0x10000000, priv.int.m.external, (priv.int.s != null) generate priv.int.s.external, mti = priv.int.m.timer, cd = cd){
  override def getClintTime(): Long = probe.cycle
  }