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@Dolu1990
Dolu1990 committed Oct 3, 2024
1 parent fa91d9e commit a44cd59
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Showing 3 changed files with 3 additions and 3 deletions.
2 changes: 1 addition & 1 deletion ext/NaxSoftware
Submodule NaxSoftware updated 4 files
+35 −0 baremetal/driver/mac_sg.h
+11 −0 baremetal/macSg/makefile
+85 −0 baremetal/macSg/src/main.c
+65 −0 baremetal/macSg/src/syscalls.c
2 changes: 1 addition & 1 deletion ext/SpinalHDL
Submodule SpinalHDL updated 9 files
+6 −0 core/src/main/scala/spinal/core/Data.scala
+3 −3 lib/src/main/scala/spinal/lib/Misc.scala
+5 −4 lib/src/main/scala/spinal/lib/Stream.scala
+20 −0 lib/src/main/scala/spinal/lib/bus/bsb/BsbPacketBuffer.scala
+15 −9 lib/src/main/scala/spinal/lib/com/eth/sg/MacSg.scala
+3 −5 lib/src/main/scala/spinal/lib/com/eth/sg/MacSgFiber.scala
+74 −54 lib/src/main/scala/spinal/lib/system/dma/sg2/DmaSgReadOnly.scala
+4 −3 tester/src/test/scala/spinal/lib/SpinalSimDmaSg2Tester.scala
+7 −4 tester/src/test/scala/spinal/lib/SpinalSimMacSgTester.scala
2 changes: 1 addition & 1 deletion src/main/scala/vexiiriscv/soc/TilelinkVexiiRiscvFiber.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -59,7 +59,7 @@ class TilelinkVexiiRiscvFiber(plugins : ArrayBuffer[Hostable]) extends Area with
val up = clint.createPort(pp.hartIds(0))
priv.mti << up.mti
priv.msi << up.msi
DataCc(up.stoptime, priv.stoptime.clockDomain(RegNext(priv.stoptime)))
DataCc(up.stoptime, priv.stoptime.clockDomain(RegNext(priv.stoptime)), initValue = U(0, 64 bits))
val time = priv.plugin.p.withRdTime generate new Area{
val timeBuffer = priv.rdtime.clockDomain(Reg(UInt(64 bits)))
DataCc(timeBuffer, clint.time)
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