add trapNextOnWrite

SpinalHDL · Jan 10, 2024 · bfe190d · bfe190d
1 parent 6d05aa7
commit bfe190d
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Showing 3 changed files with 15 additions and 3 deletions.
diff --git a/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala b/src/main/scala/vexiiriscv/execute/CsrAccessPlugin.scala
@@ -133,6 +133,17 @@ class CsrAccessPlugin(layer : LaneLayer,
 
  csrLock.await()
 
+ val trapNextOnWriteFilter = CsrListFilter(trapNextOnWrite.flatMap{
+ case e : CsrListFilter => e.mapping
+ }.toList)
+
+ onDecode(trapNextOnWriteFilter) {
+ when(onDecodeWrite) {
+ onDecodeTrap()
+ onDecodeTrapCode := TrapReason.NEXT
+ }
+ }
+
 // val useRamRead = spec.exists(_.isInstanceOf[CsrRamSpec])
 // val useRamWrite = spec.exists(_.isInstanceOf[CsrRamSpec])
 // val useRam = spec.exists(_.isInstanceOf[CsrRamSpec])

diff --git a/src/main/scala/vexiiriscv/execute/CsrService.scala b/src/main/scala/vexiiriscv/execute/CsrService.scala
@@ -31,6 +31,7 @@ trait CsrService {
  val onReadingHartIdMap = mutable.LinkedHashMap[Int, Bool]()
  val isReadingHartIdCsrMap = mutable.LinkedHashMap[(Int, Any), Bool]()
  val onWritingHartIdMap = mutable.LinkedHashMap[Int, Bool]()
+ val trapNextOnWrite = mutable.LinkedHashSet[Any]()
 
  def onDecode(csrFilter : Any, priority : Int = 0)(body : => Unit) = spec += CsrOnDecode(csrFilter, priority, () => body)
  def onDecodeException() : Unit

diff --git a/src/main/scala/vexiiriscv/memory/MmuPlugin.scala b/src/main/scala/vexiiriscv/memory/MmuPlugin.scala
@@ -9,7 +9,7 @@ import spinal.lib.misc.pipeline._
 import vexiiriscv._
 import Global._
 import spinal.lib.misc.pipeline.{NodeBaseApi, Payload}
-import vexiiriscv.execute.{CsrAccessPlugin, CsrRamService}
+import vexiiriscv.execute.{CsrAccessPlugin, CsrListFilter, CsrRamService}
 import vexiiriscv.memory.AddressTranslationPortUsage.LOAD_STORE
 import vexiiriscv.misc.{PipelineBuilderPlugin, PrivilegedPlugin, TrapReason}
 import vexiiriscv.riscv.CSR
@@ -197,13 +197,13 @@ class MmuPlugin(var spec : MmuSpec,
  csr.writeCancel(CSR.SATP, satpModeWrite =/= 0 && satpModeWrite =/= spec.satpMode)
  // csr.readWriteRam(CSR.SATP) not suported by writeCancel
 
- //TODO !!!! MISS SPEC : Changes to the sstatus fields SUM and MXR take effect immediately, without the need to execute an SFENCE.VMA instruction.
  csr.onDecode(CSR.SATP){
  csr.onDecodeTrap()
  csr.onDecodeTrapCode := TrapReason.SFENCE_VMA
-// invalidatePort.cmd.valid := True
  }
 
+ csr.trapNextOnWrite += CsrListFilter(List(CSR.MSTATUS, CSR.SSTATUS))
+
  csrLock.release()
  portsLock.await()