access more than 4GB address issue

[zjin8520]

Hi sir,

when I try to access an address which more than 4GB (write 0x12345678 to address 0x100000010, then read back), I got store/load exception, and LsuCacheless port not send out the trans. Following is the disassembly code. And I generate VexiiRiscv's command is : sbt "Test/runMain vexiiriscv.Generate --xlen 64 --with-mul --with-div --with-rva --with-rvZb --with-boot-mem-init --physical-width 64". Could you please help to check it? Thank you very much

[Dolu1990]

Hi,

I pushed in the prefetch branch an option which allow to specify the PMA via the arguements :
--region base=80000000,size=380000000,main=1,exe=1
--region base=10000000,size=10000000,main=0,exe=0
--physical-width=34

With your tests did you manualy edited the memory regions ? (else just use the prefetch branch with the arguements above)