Fix broken library vhdl_standard. #594

tests/unit/test_test_report.py

@@ -281,13 +281,11 @@ def test_dict_report_with_all_passed_tests(self):
         test_path = join(opath, TEST_OUTPUT_PATH, "unit")
         output_file_name = join(test_path, basename(self.output_file_name))
         results = Results(
-            opath, None, self._report_with_all_passed_tests(output_file_name),
+            opath, None, self._report_with_all_passed_tests(output_file_name)
         )
         report = results.get_report()
         for key, test in report.tests.items():
-            self.assertEqual(
-                basename(test.path), test.relpath,
-            )
+            self.assertEqual(basename(test.path), test.relpath)
         test0 = report.tests["passed_test0"]
         test1 = report.tests["passed_test1"]
         self.assertEqual(

tests/unit/test_ui.py

@@ -26,6 +26,7 @@
 from vunit.ostools import renew_path
 from vunit.builtins import add_verilog_include_dir
 from vunit.sim_if import SimulatorInterface
+from vunit.vhdl_standard import VHDL
 
 
 class TestUi(unittest.TestCase):
@@ -722,6 +723,20 @@ def test_add_fileset_manual_dependencies(self):
                 names(ui.get_compile_order([foo_file])), names([bar_file, foo_file])
             )
 
+    def _create_ui_with_mocked_project_add_source_file(self):
+        """
+        Helper method to create an VUnit object with a mocked project
+        to test that the Project.add_source_files method gets the correct arguments
+        """
+        ui = self._create_ui()
+        real_project = ui._project
+        fun = mock.Mock()
+        retval = mock.Mock()
+        retval.design_units = []
+        fun.return_value = retval
+        ui._project.add_source_file = fun
+        return ui, fun
+
     def test_add_source_files_has_include_dirs(self):
         file_name = "verilog.v"
         include_dirs = ["include_dir"]
@@ -732,20 +747,18 @@ def check(action):
             """
             Helper to check that project method was called
             """
-            ui = self._create_ui()
-            with mock.patch.object(ui, "_project", autospec=True) as project:
-                project.has_library.return_value = True
-                lib = ui.library("lib")
-                action(ui, lib)
-                project.add_source_file.assert_called_once_with(
-                    abspath("verilog.v"),
-                    "lib",
-                    file_type="verilog",
-                    include_dirs=all_include_dirs,
-                    defines=None,
-                    vhdl_standard=None,
-                    no_parse=False,
-                )
+            ui, add_source_file = self._create_ui_with_mocked_project_add_source_file()
+            lib = ui.add_library("lib")
+            action(ui, lib)
+            add_source_file.assert_called_once_with(
+                abspath("verilog.v"),
+                "lib",
+                file_type="verilog",
+                include_dirs=all_include_dirs,
+                defines=None,
+                vhdl_standard=VHDL.STD_2008,
+                no_parse=False,
+            )
 
         check(
             lambda ui, _: ui.add_source_files(
@@ -770,20 +783,18 @@ def check(action):
             """
             Helper to check that project method was called
             """
-            ui = self._create_ui()
-            with mock.patch.object(ui, "_project", autospec=True) as project:
-                project.has_library.return_value = True
-                lib = ui.library("lib")
-                action(ui, lib)
-                project.add_source_file.assert_called_once_with(
-                    abspath("verilog.v"),
-                    "lib",
-                    file_type="verilog",
-                    include_dirs=all_include_dirs,
-                    defines=defines,
-                    vhdl_standard=None,
-                    no_parse=False,
-                )
+            ui, add_source_file = self._create_ui_with_mocked_project_add_source_file()
+            lib = ui.add_library("lib")
+            action(ui, lib)
+            add_source_file.assert_called_once_with(
+                abspath("verilog.v"),
+                "lib",
+                file_type="verilog",
+                include_dirs=all_include_dirs,
+                defines=defines,
+                vhdl_standard=VHDL.STD_2008,
+                no_parse=False,
+            )
 
         check(lambda ui, _: ui.add_source_files(file_name, "lib", defines=defines))
         check(lambda ui, _: ui.add_source_file(file_name, "lib", defines=defines))
@@ -797,29 +808,27 @@ def test_add_source_files_has_no_parse(self):
 
         for no_parse in (True, False):
             for method in range(4):
+                ui, add_source_file = (
+                    self._create_ui_with_mocked_project_add_source_file()
+                )
+                lib = ui.add_library("lib")
 
-                ui = self._create_ui()
-                with mock.patch.object(ui, "_project", autospec=True) as project:
-                    project.has_library.return_value = True
-
-                    if method == 0:
-                        ui.add_source_files(file_name, "lib", no_parse=no_parse)
-                    elif method == 1:
-                        ui.add_source_file(file_name, "lib", no_parse=no_parse)
-                    elif method == 2:
-                        lib = ui.library("lib")
-                        lib.add_source_files(file_name, no_parse=no_parse)
-                    elif method == 3:
-                        lib = ui.library("lib")
-                        lib.add_source_file(file_name, no_parse=no_parse)
-
-                    project.add_source_file.assert_called_once_with(
+                if method == 0:
+                    ui.add_source_files(file_name, "lib", no_parse=no_parse)
+                elif method == 1:
+                    ui.add_source_file(file_name, "lib", no_parse=no_parse)
+                elif method == 2:
+                    lib.add_source_files(file_name, no_parse=no_parse)
+                elif method == 3:
+                    lib.add_source_file(file_name, no_parse=no_parse)
+
+                    add_source_file.assert_called_once_with(
                         abspath("verilog.v"),
                         "lib",
                         file_type="verilog",
                         include_dirs=all_include_dirs,
                         defines=None,
-                        vhdl_standard=None,
+                        vhdl_standard=VHDL.STD_2008,
                         no_parse=no_parse,
                     )
 

vunit/ui/library.py

@@ -11,6 +11,7 @@
 from os.path import abspath
 from glob import glob
 from fnmatch import fnmatch
+from ..vhdl_standard import VHDL
 from ..sim_if import is_string_not_iterable
 from ..source_file import file_type_of, FILE_TYPES, VERILOG_FILE_TYPES
 from ..builtins import add_verilog_include_dir
@@ -266,7 +267,7 @@ def add_source_file(  # pylint: disable=too-many-arguments
             file_type=file_type,
             include_dirs=include_dirs,
             defines=defines,
-            vhdl_standard=vhdl_standard,
+            vhdl_standard=self._which_vhdl_standard(vhdl_standard),
             no_parse=no_parse,
         )
         # To get correct tb_path generic
@@ -355,3 +356,13 @@ def get_test_benches(self, pattern="*", allow_empty=False):
             allow_empty,
             "No test benches found within library %s" % self._library_name,
         )
+
+    def _which_vhdl_standard(self, vhdl_standard):
+        """
+        Return default vhdl_standard if the argument is None
+        The argument is a string from the user
+        """
+        if vhdl_standard is None:
+            return self._project.get_library(self._library_name).vhdl_standard
+
+        return VHDL.standard(vhdl_standard)