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Have AIECtrlPacketToDmaPass create dynamic MemRefType for ctrl packet stream #1776

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merged 4 commits into from
Sep 18, 2024
Merged

Have AIECtrlPacketToDmaPass create dynamic MemRefType for ctrl packet stream #1776

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6232f02
Have AIECtrlPacketToDmaPass figure out the ctrl packet stream size, i…
erwei-xilinx Sep 18, 2024
83934c6
Update mlir unit tests
erwei-xilinx Sep 18, 2024
cb52dac
Change cost code to allocate ctrl pkt stream memory based on stream size
erwei-xilinx Sep 18, 2024
8013008
Using dynamic shape for MemRefType for ctrl pkt stream
erwei-xilinx Sep 18, 2024
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5 changes: 3 additions & 2 deletions lib/Dialect/AIEX/IR/AIEXDialect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -347,8 +347,9 @@ LogicalResult AIEX::NpuDmaMemcpyNdOp::verify() {
if (buffer.getElementTypeBitWidth() > addressGranularity) {
return emitOpError("Maximum element bit width allowed is ")
<< addressGranularity << "bits. ";
} else if ((buffer.getNumElements() * buffer.getElementTypeBitWidth()) <
addressGranularity) {
} else if (buffer.hasStaticShape() &&
(buffer.getNumElements() * buffer.getElementTypeBitWidth()) <
addressGranularity) {
return emitOpError("Minimum data transfer size required is ")
<< addressGranularity << "bits. ";
}
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4 changes: 3 additions & 1 deletion lib/Dialect/AIEX/Transforms/AIECtrlPacketToDma.cpp
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Expand Up @@ -76,8 +76,10 @@ struct AIECtrlPacketToDmaPass : AIECtrlPacketToDmaBase<AIECtrlPacketToDmaPass> {
auto newSeq =
builder.create<AIEX::RuntimeSequenceOp>(loc, f.getSymNameAttr());
newSeq.getBody().push_back(new Block);

// Using dynamic shape for ctrl pkt stream.
auto ctrlPktMemrefType = MemRefType::get(
SmallVector<int64_t>{1024}, IntegerType::get(ctx, 32), nullptr, 0);
ShapedType::kDynamic, IntegerType::get(ctx, 32), nullptr, 0);
auto newBlockArg = newSeq.getBody().addArgument(ctrlPktMemrefType, loc);
builder.setInsertionPointToStart(&newSeq.getBody().front());

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12 changes: 6 additions & 6 deletions test/dialect/AIEX/ctrl_pkt_to_dma.mlir
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Expand Up @@ -13,13 +13,13 @@
// transforms control packet ops to dma memcpy ops and sync ops.

// CHECK-LABEL: aie.device(npu1_1col) {
// CHECK: aiex.runtime_sequence(%[[ARG0:.*]]: memref<1024xi32>) {
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 1, 1, 2][0, 0, 0, 1], packet = <pkt_type = 0, pkt_id = 15>) {id = 0 : i64, issue_token = true, metadata = @ctrlpkt_col0_mm2s_chan0} : memref<1024xi32>
// CHECK: aiex.runtime_sequence(%[[ARG0:.*]]: memref<?xi32>) {
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 1, 1, 2][0, 0, 0, 1], packet = <pkt_type = 0, pkt_id = 15>) {id = 0 : i64, issue_token = true, metadata = @ctrlpkt_col0_mm2s_chan0} : memref<?xi32>
// CHECK: aiex.npu.sync {channel = 0 : i32, column = 0 : i32, column_num = 1 : i32, direction = 1 : i32, row = 0 : i32, row_num = 1 : i32}

aie.device(npu1_1col) {
%tile_0_0 = aie.tile(0, 0) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 15>}
aiex.runtime_sequence(%arg0: memref<2048xi32>) {
aiex.runtime_sequence() {
aiex.control_packet {address = 126976 : ui32, data = array<i32: 1024>, opcode = 0 : i32, stream_id = 0 : i32}
}
aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0)
Expand All @@ -29,14 +29,14 @@ aie.device(npu1_1col) {
// -----

// CHECK-LABEL: aie.device(npu1_1col) {
// CHECK: aiex.runtime_sequence(%[[ARG0:.*]]: memref<1024xi32>) {
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 1, 1, 2][0, 0, 0, 1], packet = <pkt_type = 0, pkt_id = 27>) {id = 0 : i64, issue_token = true, metadata = @ctrlpkt_col0_mm2s_chan0} : memref<1024xi32>
// CHECK: aiex.runtime_sequence(%[[ARG0:.*]]: memref<?xi32>) {
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 1, 1, 2][0, 0, 0, 1], packet = <pkt_type = 0, pkt_id = 27>) {id = 0 : i64, issue_token = true, metadata = @ctrlpkt_col0_mm2s_chan0} : memref<?xi32>
// CHECK: aiex.npu.sync {channel = 0 : i32, column = 0 : i32, column_num = 1 : i32, direction = 1 : i32, row = 0 : i32, row_num = 1 : i32}

aie.device(npu1_1col) {
%tile_0_0 = aie.tile(0, 0)
%tile_0_2 = aie.tile(0, 2) {controller_id = #aie.packet_info<pkt_type = 0, pkt_id = 27>}
aiex.runtime_sequence(%arg0: memref<2048xi32>) {
aiex.runtime_sequence() {
aiex.control_packet {address = 2301952 : ui32, data = array<i32: 0>, opcode = 0 : i32, stream_id = 0 : i32}
}
aie.shim_dma_allocation @ctrlpkt_col0_mm2s_chan0(MM2S, 0, 0)
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3 changes: 1 addition & 2 deletions test/npu-xrt/ctrl_packet_reconfig/test.cpp
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Expand Up @@ -23,7 +23,6 @@

constexpr int IN_SIZE = 64 * 64;
constexpr int OUT_SIZE = 64 * 64;
constexpr int CTRL_IN_SIZE = 1024;

#define IN_DATATYPE int8_t
#define OUT_DATATYPE int8_t
Expand Down Expand Up @@ -89,7 +88,7 @@ int main(int argc, const char *argv[]) {
XRT_BO_FLAGS_HOST_ONLY, kernel.group_id(3));
auto bo_out = xrt::bo(device, OUT_SIZE * sizeof(OUT_DATATYPE),
XRT_BO_FLAGS_HOST_ONLY, kernel.group_id(4));
auto bo_ctrlpkt = xrt::bo(device, CTRL_IN_SIZE * sizeof(int32_t),
auto bo_ctrlpkt = xrt::bo(device, ctrlPackets.size() * sizeof(int32_t),
XRT_BO_FLAGS_HOST_ONLY, kernel.group_id(3));

IN_DATATYPE *bufInA = bo_inA.map<IN_DATATYPE *>();
Expand Down
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