Fix the creation of implicit clock wires (#144)

Corrects a mistake where non-existent wires were created for chips with 4 quadrants. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
YosysHQ · Dec 20, 2022 · 20af410 · 20af410
1 parent 5646882
commit 20af410
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/apycula/clock_fuzzer.py b/apycula/clock_fuzzer.py
@@ -267,7 +267,7 @@ def spine_aliases(quads, dests, clks):
 def add_rim(rows, cols, spine_row):
     if 1 in rows:
         rows.add(0)
-    if max(rows) > spine_row:
+    if max(rows) > spine_row and spine_row != 1:
         rows.update({row for row in range(max(rows) + 1, db.rows)})
     if 1 in cols:
         cols.add(0)