Add parameter check and DUTY handling #134
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As stated in the documentation: "For example, when the phase shift setting is "0" (00000), 50% duty cycle will be "8" (1000). If the phase shift setting is "180", the 50%, the 50% duty cycle setting is "0" (0000)." As there are fuses for all DUTY values at the moment we do not check for special missing cases 0, 1, 15. In the case of static divider assignment, check the permissible frequency range for the desired chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
It's more honest to call it a formula to approximate the combination of fuses for different frequencies as we are unlikely to ever find out exactly how the PLL internals of these chips are set up. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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I think the PLL examples need to be reworked so that several images with different output frequencies are generated for each board. hm... |
The frequencies used are the most appropriate for the quartz resonators of the different boards. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Having dedicated ports for dividers makes configuration on the move much easier. Examples have been added for dynamic PLL reconfiguration. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Convert some numerical attribute values to strings and combine port wires. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Adding a flip-flop to the PLL example so there is no swearing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Also an illustration of disabling ports in the example (reset, reset_p, clkouto and ckoutpd3 are not used). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
When unpacking, all unused ports are removed. Also: - RESET and RESET_P inputs are disabled by default; - allowing feedback via dedicated pin and general routing. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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About support for different feedback and clkin routes - gowin_pack of course does not do routing, it just removes restrictions on usage, the routes themselves are created in nextpnr :) |
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
If the input MUX (for CLKIN input) is in a state where all its 3 programming bits are 0, the PLL is assumed to be disabled. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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As stated in the documentation: "For example, when the phase shift setting is "0" (00000), 50% duty cycle will be "8" (1000). If the phase shift setting is "180", the 50%, the 50% duty cycle setting is "0" (0000)."
As there are fuses for all DUTY values at the moment we do not check for special missing cases 0, 1, 15.
In the case of static divider assignment, check the permissible frequency range for the desired chip.
Signed-off-by: YRabbit rabbit@yrabbit.cyou