Change the IO coding to synthetic #177

yrabbit · 2023-05-19T09:19:16Z

The new coding system uses a logicinfo table to search for the right fuzes by given combinations of attributes.
Actually required bits are taken from vendor's longval tables. The same tables are used to decode binary images.

tiled_fuzzer.py calls the vendor compiler only once to get an empty image template.

All references to IO coding bits, including standards, are removed from the base structure.
Removed fuzzing IO.
Removed fuzzing corner bank cells - their own table is used for them.
Removed fuzzing of dual-purpose pins - their own table is used for them.
Real LVDS primitives TLVDS_IBUF, TLVDS_TBUF and TLVDS_IOBUF are implemented.
All emulated LVDS primitives are implemented: ELVDS_IBUF, ELVDS_OBUF, ELVDS_TBUF, ELVDS_IOBUF.
All new primitives can connect with IOLOGIC.
The OEN port of the I/O primitives (including differential ones) can be controlled by IOLOGIC.
Added detection of gross user errors like placing TLVDS in place of the emulated one.
It is possible to use as a differential special simplified IO elements located on the 6th row in the chips GW1N-1 and GW1NZ-1, but here may require additional research and in general the other pins should be enough.

The new coding system uses a logicinfo table to search for the right fuzes by given combinations of attributes. Actually required bits are taken from vendor's longval tables. The same tables are used to decode binary images. tiled_fuzzer.py calls the vendor compiler only once to get an empty image template. * All references to IO coding bits, including standards, are removed from the base structure. * Removed fuzzing IO. * Removed fuzzing corner bank cells - their own table is used for them. * Removed fuzzing of dual-purpose pins - their own table is used for them. * Real LVDS primitives TLVDS_IBUF, TLVDS_TBUF and TLVDS_IOBUF are implemented. * All emulated LVDS primitives are implemented: ELVDS_IBUF, ELVDS_OBUF, ELVDS_TBUF, ELVDS_IOBUF. * All new primitives can connect with IOLOGIC. * The OEN port of the I/O primitives (including differential ones) can be controlled by IOLOGIC. * Added detection of gross user errors like placing TLVDS in place of the emulated one. * It is possible to use as a differential special simplified IO elements located on the 6th row in the chips GW1N-1 and GW1NZ-1, but here may require additional research and in general the other pins should be enough. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

yrabbit · 2023-05-19T09:31:21Z

Forgot:

New test cases have been added.
In the old examples, OBUF is replaced by TBUF, which reacts to the press of a button to demonstrate the workability of these primitives.

pepijndevos

Haven't tried it out yet but visual inspection looks good to me. Really love deleting code from tiled_fuzzer.

This doesn't change the chipdb format, or does it? Just want to make sure that if the final DB is different we maybe bump the db number, and if it isn't that we can compare the DB before and after this PR to make sure there are no unintended changes.

I'll try out the code tomorrow. Exciting!

apycula/chipdb.py

pepijndevos · 2023-05-27T15:49:29Z

apycula/pindef.py

@@ -109,19 +109,19 @@ def get_diff_cap_info(device, package, special_pins=False):
 is_diff = 'DIFF' in pin.keys()
 if not is_diff:
 res[str(pin['NAME'])] = (is_diff, is_true_lvds, is_positive)
- cotinue


This led me to believe that this situation never occurs in principle, otherwise it would have been discovered a long time ago, but left it for now just in case :)

pepijndevos · 2023-05-27T15:58:05Z

apycula/tiled_fuzzer.py

-
- # bank modes
- fse_banks(fse, db, corners)
+ fse_iob(fse, db, pin_locations, diff_cap_info, locations);

 chipdb.dat_portmap(dat, db, device)


I'm thinking if it makes sense to restructure chipdb assembly a bit now. It used to be that here we extract data from fse and dat files, do fuzzing, and then feed it to the next stage doing clock stuff and such. I think it's fine as it is, but maybe there is opportunity to restructure things a bit. This file is hardly "tiled_fuzzer" any more haha

there is still a call to the IDE compiler to get an empty image;) But yes, restructuring is called for.

pepijndevos · 2023-05-27T16:01:12Z

apycula/gowin_pack.py

- if k not in iologic_attrids.keys():
- print(f'XXX add {k} key handle')
+ if k not in attrids.iologic_attrids.keys():
+ print(f'XXX IOLOGIC: add {k} key handle')


Another idea that I don't think is really required but could be interesting to do eventually is to use the logging module instead of printing, so we could use logging.warn here or something like that.

That's for sure. print is very inconvenient because of the lack of structuring of messages - this XXX is a trick to be able to then search by type of messages in the output otherwise I just skipped my own debugging information :) But this is exactly a crutch.

yrabbit · 2023-05-27T20:14:19Z

This doesn't change the chipdb format, or does it? Just want to make sure that if the final DB is different we maybe bump the db number, and if it isn't that we can compare the DB before and after this PR to make sure there are no unintended changes.

Yes, the structure has changed to throw out unnecessary and irrelevant information about IO.
From nextpnr side, however, it is unnoticeable - the structure of exported data has not changed.

+++ b/apycula/chipdb.py
@@ -16,22 +16,6 @@ mode_attr_sep = '&'
 # can be either tiles or bits within tiles
 Coord = Tuple[int, int]

-# IOB flag descriptor
-# bitmask and possible values
-@dataclass
-class IOBFlag:
-    mask: Set[Coord] = field(default_factory = set)
-    options: Dict[str, Set[Coord]] = field(default_factory = dict)
-
-# IOB mode descriptor
-# bits and flags
-# encode bits include all default flag values
-@dataclass
-class IOBMode:
-    encode_bits: Set[Coord] = field(default_factory = set)
-    decode_bits: Set[Coord] = field(default_factory = set)
-    flags: Dict[str, IOBFlag] = field(default_factory = dict)
-
 @dataclass
 class Bel:
     """Respresents a Basic ELement
@@ -39,18 +23,12 @@ class Bel:
     and the specified portmap"""
     # there can be zero or more flags
     flags: Dict[Union[int, str], Set[Coord]] = field(default_factory=dict)
-    # { iostd: { mode : IOBMode}}
-    iob_flags: Dict[str, Dict[str, IOBMode]] = field(default_factory=dict)
-    lvcmos121518_bits: Set[Coord] = field(default_factory = set)
     # this Bel is IOBUF and needs routing to become IBUF or OBUF
     simplified_iob: bool = field(default = False)
     # differential signal capabilities info
     is_diff:      bool = field(default = False)
     is_true_lvds: bool = field(default = False)
-    # banks
-    bank_mask: Set[Coord] = field(default_factory=set)
-    bank_flags: Dict[str, Set[Coord]] = field(default_factory=dict)
-    bank_input_only_modes: Dict[str, str] = field(default_factory=dict)
+    is_diff_p:    bool = field(default = False)
     # there can be only one mode, modes are exclusive
     modes: Dict[Union[int, str], Set[Coord]] = field(default_factory=dict)
     portmap: Dict[str, str] = field(default_factory=dict)

It was used to minimize the bit representation of various I/O cell features, but is no longer relevant due to the fact that bits are no longer defined by fuzzing and are not stored in the database. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

pepijndevos · 2023-05-28T18:22:28Z

I tested a couple of examples and they all work so far. Except attosoc of course...

pepijndevos · 2023-05-28T18:36:17Z

Hmmm I tried to compare the chipdbs and it seems they are largely the same which is good news but there are a few differences, and I want to make sure they are expected. Need to try to remember what these values mean.
attr.txt
master.txt

pepijndevos · 2023-05-28T18:45:59Z

It seems to be only portmaps that are slightly different. If this makes sense to you, I think it's good to merge.

yrabbit · 2023-05-28T22:28:05Z

It seems to be only portmaps that are slightly different. If this makes sense to you, I think it's good to merge.

It makes sense and the portmap is not really different - just that some Bels are unloaded in a different order (sort of like IOBB was ahead of IOBA) and naturally drag their portmap with them.

I don't know why this thing happens, but it doesn't affect nextpnr in any way :)

yrabbit requested a review from pepijndevos May 20, 2023 06:24

mole99 mentioned this pull request May 20, 2023

nextpnr-gowin cannot route OSER10 to ELVDS_OBUF YosysHQ/nextpnr#1147

Open

pepijndevos approved these changes May 27, 2023

View reviewed changes

Remove auxiliary function

55b1012

It was used to minimize the bit representation of various I/O cell features, but is no longer relevant due to the fact that bits are no longer defined by fuzzing and are not stored in the database. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

pepijndevos merged commit d350cb7 into YosysHQ:master May 29, 2023

yrabbit deleted the io-attrs branch May 29, 2023 06:42

This was referenced May 29, 2023

Add support for emulated differential output (ELVDS) #159

Closed

gowin_pack fails on nano9k with strange LVCMOS18 error #158

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Change the IO coding to synthetic #177

Change the IO coding to synthetic #177

yrabbit commented May 19, 2023

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Change the IO coding to synthetic #177

Change the IO coding to synthetic #177

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