BSRAM. Corrective action. #252
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Chips that have features in the implementation of BSRAM are marked with special flags, to which nextpnr reacts by adding corrective primitives such as LUTs and DFFs and changing routing if necessary. Currently this is a fix for WRE-CE signals in Single Port BSRAM and a fix for READ_MODE=1'b1 (pipeline). A .CST file is also added for the reduced SZFPGA board - it uses a GW1N-9 chip in a 48-pin package versus a “full-fledged” SZFPGA with a GW1NR-9 chip in a 144-pin package. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Chips that have features in the implementation of BSRAM are marked with special flags, to which nextpnr reacts by adding corrective primitives such as LUTs and DFFs and changing routing if necessary.
Currently this is a fix for WRE-CE signals in Single Port BSRAM and a fix for READ_MODE=1'b1 (pipeline).
A .CST file is also added for the reduced SZFPGA board - it uses a GW1N-9 chip in a 48-pin package versus a “full-fledged” SZFPGA with a GW1NR-9 chip in a 144-pin package.