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Merge pull request #72 from YosysHQ/micko/drop_ilang
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Remove references to ilang
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jix authored Nov 8, 2024
2 parents f3e4ef8 + b3bc9c8 commit 93bf4df
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Showing 6 changed files with 21 additions and 21 deletions.
26 changes: 13 additions & 13 deletions src/eqy.py
Original file line number Diff line number Diff line change
Expand Up @@ -297,7 +297,7 @@ def build_gate_gold(args, cfg, job):
print("opt_clean", file=f)
print("check -initdrv", file=f)
print("setundef -undriven -undef", file=f)
print("write_ilang {}/gold.il".format(args.workdir), file=f)
print("write_rtlil {}/gold.il".format(args.workdir), file=f)
with open(args.workdir + "/gate.ys", "w") as f:
for line in cfg.gate:
print(line, file=f)
Expand All @@ -306,7 +306,7 @@ def build_gate_gold(args, cfg, job):
print("opt_clean", file=f)
print("check -initdrv", file=f)
print("setundef -undriven -undef", file=f)
print("write_ilang {}/gate.il".format(args.workdir), file=f)
print("write_rtlil {}/gate.il".format(args.workdir), file=f)

gold_task = EqyTask(job, "read_gold", [], "{yosys}{gopt} -ql {workdir}/gold.log {workdir}/gold.ys".format(
yosys=args.exe_paths["yosys"], gopt=" -g" if args.debugmode else "", workdir=args.workdir))
Expand All @@ -326,11 +326,11 @@ def build_get_ids(args, cfg, job):
plugin_path = root_path() # for development
with open(args.workdir + "/get_ids.ys", "w") as f:
print("plugin -i {}/eqy_combine.so".format(plugin_path), file=f)
print("read_ilang {}/gold.il".format(args.workdir), file=f)
print("read_rtlil {}/gold.il".format(args.workdir), file=f)
print("uniquify", file=f)
print("hierarchy", file=f)
print("design -stash gold", file=f)
print("read_ilang {}/gate.il".format(args.workdir), file=f)
print("read_rtlil {}/gate.il".format(args.workdir), file=f)
print("uniquify", file=f)
print("hierarchy", file=f)
print("design -stash gate", file=f)
Expand Down Expand Up @@ -374,11 +374,11 @@ def build_recode(args, ctx, job):
plugin_path = root_path() # for development
with open(args.workdir + "/recode.ys", "w") as f:
print("plugin -i {}/eqy_recode.so".format(plugin_path), file=f)
print("read_ilang {}/gold.il".format(args.workdir), file=f)
print("read_rtlil {}/gold.il".format(args.workdir), file=f)
print("design -stash gold", file=f)
print("read_ilang {}/gate.il".format(args.workdir), file=f)
print("read_rtlil {}/gate.il".format(args.workdir), file=f)
print("{dbg}eqy_recode -recode {wd}/recode.ids".format(dbg="debug " if args.debugmode else "", wd=args.workdir), file=f)
print("write_ilang {}/gate_recoded.il".format(args.workdir), file=f)
print("write_rtlil {}/gate_recoded.il".format(args.workdir), file=f)

recode_task = EqyTask(job, "recode", [], "{yosys}{gopt} -ql {workdir}/recode.log {workdir}/recode.ys".format(
yosys=args.exe_paths["yosys"], gopt=" -g" if args.debugmode else "", workdir=args.workdir))
Expand All @@ -396,16 +396,16 @@ def build_combined(args, cfg, job):
plugin_path = root_path() # for development
with open(args.workdir + "/combine.ys", "w") as f:
print("plugin -i {}/eqy_combine.so".format(plugin_path), file=f)
print("read_ilang {}/gold.il".format(args.workdir), file=f)
print("read_rtlil {}/gold.il".format(args.workdir), file=f)
print("uniquify", file=f)
print("hierarchy", file=f)
print("design -stash gold", file=f)
print("read_ilang {}/gate_recoded.il".format(args.workdir), file=f)
print("read_rtlil {}/gate_recoded.il".format(args.workdir), file=f)
print("uniquify", file=f)
print("hierarchy", file=f)
print("design -stash gate", file=f)
print("{dbg}eqy_combine -gold_ids {wd}/gold.ids -gate_ids {wd}/gate_recoded.ids".format(dbg="debug " if args.debugmode else "", wd=args.workdir), file=f)
print("write_ilang {}/combined.il".format(args.workdir), file=f)
print("write_rtlil {}/combined.il".format(args.workdir), file=f)

combine_task = EqyTask(job, "combine", [], "{yosys}{gopt} -ql {workdir}/combine.log {workdir}/combine.ys".format(
yosys=args.exe_paths["yosys"], gopt=" -g" if args.debugmode else "", workdir=args.workdir))
Expand Down Expand Up @@ -742,7 +742,7 @@ def make_partitions(args, cfg, job):
plugin_path = root_path() # for development
with open(args.workdir + "/partition.ys", "w") as f:
print("plugin -i {}/eqy_partition.so".format(plugin_path), file=f)
print("read_ilang combined.il".format(args.workdir), file=f)
print("read_rtlil combined.il".format(args.workdir), file=f)
if cfg.options.insbuf:
print("insbuf -chain", file=f)
print("{dbg}eqy_partition -matched_ids matched.ids -partition_ids partition.ids".format(dbg="debug " if args.debugmode else ""), file=f)
Expand Down Expand Up @@ -889,7 +889,7 @@ def write(self, job, partition):
with open(self.path(partition.name, "run.ys"), "w") as ys_f:
print(f"verilog_defaults -add -D CHECK_OUTPUTS", file=ys_f)
print(f"read_verilog -sv ../../../partitions/{partition.name}.sv", file=ys_f)
print(f"read_ilang ../../../partitions/{partition.name}.il", file=ys_f)
print(f"read_rtlil ../../../partitions/{partition.name}.il", file=ys_f)
print(f"hierarchy -top miter; proc; chformal -cover -remove", file=ys_f)
print("async2sync", file=ys_f) # async2sync after a user script clk2fflogic is a noop
print(f"formalff -clk2ff -ff2anyinit gate.{partition.name}", file=ys_f)
Expand Down Expand Up @@ -930,7 +930,7 @@ def write(self, job, partition):
[script]
verilog_defaults -add -D CHECK_OUTPUTS
read_verilog -sv ../../../../../partitions/{partition.name}.sv
read_ilang ../../../../../partitions/{partition.name}.il
read_rtlil ../../../../../partitions/{partition.name}.il
hierarchy -top miter; proc
"""[1:-1]), file=sby_f)

Expand Down
8 changes: 4 additions & 4 deletions src/eqy_job.py
Original file line number Diff line number Diff line change
Expand Up @@ -391,7 +391,7 @@ def warning(self, logmessage):
# print("opt -keepdc -fast", file=f)
# print("check", file=f)
# print("hierarchy -simcheck", file=f)
# print("write_ilang ../model/design{}.il".format("" if model_name == "base" else "_nomem"), file=f)
# print("write_rtlil ../model/design{}.il".format("" if model_name == "base" else "_nomem"), file=f)
#
# task = SbyTask(self, model_name, [],
# "cd {}/src; {} -ql ../model/design{s}.log ../model/design{s}.ys".format(self.workdir, self.exe_paths["yosys"],
Expand All @@ -403,7 +403,7 @@ def warning(self, logmessage):
# if re.match(r"^smt2(_syn)?(_nomem)?(_stbv|_stdt)?$", model_name):
# with open("{}/model/design_{}.ys".format(self.workdir, model_name), "w") as f:
# print("# running in {}/model/".format(self.workdir), file=f)
# print("read_ilang design{}.il".format("_nomem" if "_nomem" in model_name else ""), file=f)
# print("read_rtlil design{}.il".format("_nomem" if "_nomem" in model_name else ""), file=f)
# if "_syn" in model_name:
# print("techmap", file=f)
# print("opt -fast", file=f)
Expand All @@ -427,7 +427,7 @@ def warning(self, logmessage):
# if re.match(r"^btor(_syn)?(_nomem)?$", model_name):
# with open("{}/model/design_{}.ys".format(self.workdir, model_name), "w") as f:
# print("# running in {}/model/".format(self.workdir), file=f)
# print("read_ilang design{}.il".format("_nomem" if "_nomem" in model_name else ""), file=f)
# print("read_rtlil design{}.il".format("_nomem" if "_nomem" in model_name else ""), file=f)
# print("flatten", file=f)
# print("setundef -undriven -anyseq", file=f)
# if "_syn" in model_name:
Expand All @@ -452,7 +452,7 @@ def warning(self, logmessage):
# if model_name == "aig":
# with open("{}/model/design_aiger.ys".format(self.workdir), "w") as f:
# print("# running in {}/model/".format(self.workdir), file=f)
# print("read_ilang design_nomem.il", file=f)
# print("read_rtlil design_nomem.il", file=f)
# print("flatten", file=f)
# print("setundef -undriven -anyseq", file=f)
# print("setattr -unset keep", file=f)
Expand Down
2 changes: 1 addition & 1 deletion src/eqy_partition.cc
Original file line number Diff line number Diff line change
Expand Up @@ -1247,7 +1247,7 @@ struct Partition
sby_file << "verilog_defaults -add -D DIRECT_CROSS_POINTS\n";
sby_file << "# verilog_defaults -add -D ASSUME_DEFINED_INPUTS\n";
sby_file << "read_verilog -sv ../../" << partname.substr(1) << ".sv\n";
sby_file << "read_ilang ../../" << partname.substr(1) << ".il\n";
sby_file << "read_rtlil ../../" << partname.substr(1) << ".il\n";
sby_file << "hierarchy -top miter; proc\n";
sby_file << "formalff -clk2ff -ff2anyinit gate." << partname.substr(1) << "\n";
sby_file << "setundef -anyseq gate." << partname.substr(1) << "\n";
Expand Down
2 changes: 1 addition & 1 deletion tests/plugin/partition_matching_gate_not_found.ys
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
logger -expect error "Could not find matching gate for module gold.counter" 1
read_ilang data/counter_combined.il
read_rtlil data/counter_combined.il
insbuf -chain
delete gate.counter
eqy_partition -matched_ids data/counter_matched.ids -partition_ids data/counter_partition.ids -write_fragments
2 changes: 1 addition & 1 deletion tests/plugin/partition_no_matched.ys
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
logger -expect error "No matched IDs for module counter." 1
read_ilang data/counter_combined.il
read_rtlil data/counter_combined.il
insbuf -chain
eqy_partition -matched_ids data/matched_empty.ids -partition_ids data/counter_partition.ids
2 changes: 1 addition & 1 deletion tests/plugin/partition_write_fragments.ys
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
exec -- rm -rf fragments/ modules/ partitions/ partition.list fragment.list
exec -- mkdir -p fragments modules partitions
read_ilang data/counter_combined.il
read_rtlil data/counter_combined.il
insbuf -chain
eqy_partition -matched_ids data/counter_matched.ids -partition_ids data/counter_partition.ids -write_fragments
exec -- rm -rf fragments/ modules/ partitions/ partition.list fragment.list

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