gowin: Himbaechel. Handling of disabled units

Using extra cell functions to mark disabled units using the PLL example. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
YosysHQ · Aug 21, 2023 · 9bfb0cf · 9bfb0cf
1 parent cf7dd93
commit 9bfb0cf
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Showing 3 changed files with 15 additions and 6 deletions.
diff --git a/himbaechel/uarch/gowin/globals.cc b/himbaechel/uarch/gowin/globals.cc
@@ -190,6 +190,10 @@ struct GowinGlobalRouter
  NPNR_ASSERT(driver.cell->bel != BelId());
  IdStringList pin_func = gwu.get_pin_funcs(driver.cell->bel);
  for (size_t i = 0; i < pin_func.size(); ++i) {
+ if (ctx->debug) {
+ log_info("bel:%s, pin func: %lu:%s\n", ctx->nameOfBel(driver.cell->bel), i,
+ pin_func[i].str(ctx).c_str());
+ }
  if (pin_func[i].str(ctx).rfind("GCLKT", 0) == 0) {
  if (ctx->debug) {
  log_info("Clock pin:%s:%s\n", ctx->getBelName(driver.cell->bel).str(ctx).c_str(),

diff --git a/himbaechel/uarch/gowin/gowin.cc b/himbaechel/uarch/gowin/gowin.cc
@@ -113,14 +113,10 @@ void GowinImpl::init(Context *ctx)
  }
  }
 
- if (ctx->debug) {
- log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
- }
+ // log_info("packages:%ld\n", ctx->chip_info->packages.ssize());
  for (int i = 0; i < ctx->chip_info->packages.ssize(); ++i) {
  if (IdString(ctx->chip_info->packages[i].name) == package_idx) {
- if (ctx->debug) {
- log_info("i:%d %s\n", i, package_idx.c_str(ctx));
- }
+ // log_info("i:%d %s\n", i, package_idx.c_str(ctx));
  ctx->package_info = &ctx->chip_info->packages[i];
  break;
  }

diff --git a/himbaechel/uarch/gowin/gowin_arch_gen.py b/himbaechel/uarch/gowin/gowin_arch_gen.py
@@ -565,9 +565,18 @@ def create_pll_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tdesc
  tiletype = f"{typename}_{ttyp}"
  if tdesc.sfx != 0:
  tiletype += f"_{tdesc.sfx}"
+
+ # disabled PLLs
+ if tdesc.extra_func and 'disabled' in tdesc.extra_func and 'PLL' in tdesc.extra_func['disabled']:
+ tiletype += '_disabled'
+ tt = chip.create_tile_type(tiletype)
+ tt.extra_data = TileExtraData(chip.strs.id(typename))
+ tdesc.tiletype = tiletype
+ return tt
  tt = chip.create_tile_type(tiletype)
  tt.extra_data = TileExtraData(chip.strs.id(typename))
 
+
  # wires
  if chip.name == 'GW1NS-4':
  pll_name = 'PLLVR'