Gd32v Support

[kassane]

References

SVD - Sipeed
GigaDevice device-info
Sipeed -Logan Nano
Manual - Firmware Library (PDF)

[kassane]

cc: @mattnite @vesim987

Is it possible to automate the translation or read the start.S file in zig build or microzig?
I found the files needed to support the chip in the GD32v firmware libraries ¹, but am having difficulty converting them.
And comparing on the rust solution ² for this I was in doubt of the real support with llvm.

[kassane]

Status

• Logan Nano board added

By adding some changes you find errors in the api during the build:

Uart error:

./src/core/uart.zig:6:28: error: container '.chip' has no member called 'Uart'
    const SystemUart = chip.Uart(index);
                           ^
./src/modules/boards/logan-nano/logan-nano.zig:60:29: note: called from here
    const uart0 = micro.Uart(0).getOrInit(.{
                            ^
./src/modules/boards/logan-nano/logan-nano.zig:59:44: note: called from here
pub fn debugWrite(string: []const u8) void {

Pin error:

./src/core/pin.zig:22:13: error: container '.chip' has no member called 'parsePin'
        chip.parsePin(@field(board.pin_map, spec))
            ^
./tests/blinky.zig:9:36: note: called from here
        .@"Logan Nano" => micro.Pin("PC13"), // error in 'parsePin'
                                   ^
./tests/blinky.zig:4:17: note: called from here
const led_pin = if (micro.config.has_board)

[widlarizer]

I suggest writing a small HAL for STM32F103 first. It is better documented, the GD32VF is a binary compatible clone. Right now your PR uses F303 HAL which is incompatible, for example, instead of a single GPIO mode register there are two with different fields, so it's not just renaming registers that you have to make it work
By the way, it's Longan, not Logan

[kassane]

Hi @ekliptik

Nice tip! I already made some improvements, however didn't have time to validate and send the new commit containing these improvements and including the board name was fixed.

But thanks for the review!

[mattnite]

@kassane looks like some unused parameters are causing the build to fail

[kassane]

@kassane looks like some unused parameters are causing the build to fail

fix

[mattnite]

are you able to confirm that this is how interrupts work on the chip, and is it consistent with other risc chips?

[kassane]

are you able to confirm that this is how interrupts work on the chip, and is it consistent with other risc chips?

First, you can't confuse gd32 (bluepill clone) with gd32v even though the pinouts are compatible. The main difference is that gd32v has a higher clock speed.

The IRQ mechanism (ECLIC) of this device is unique to the Nuclei manufacturer (core Bumblebee) since RISC-V has no default interrupt mechanism.
So far the interrupt implementation is not finished as it would need to use pieces of code from the official SDK and toolchain (nuclei-gcc fork), even attach an assembly file as it was done in the rust project (see this).

The SVD provided is also not complete, many complain about certain details like undeclared core timer.
And regz did not translate it completely (missing clusters), so it will have to be done manually with the respective time.

Reference

• ECLIC - Nuclei doc

[mattnite]

okay if that's the case then we shouldn't be putting arm interrupt table code in the risc processor code, similar to how we add a skip for the uart example, please add a skip mechanism for the interrupt example.

[mattnite]

🙏 thanks for getting the first riscv patch in!

[kassane]

🙏 thanks for getting the first riscv patch in!

Thank you for the patience. 😅