armbian · ColorfulRhino · Jun 14, 2024 · Jun 12, 2024 · Jun 12, 2024 · Jun 13, 2024
@@ -0,0 +1,347 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:42 +0200
+Subject: media: dt-bindings: rk3568-vepu: Add RK3588 VEPU121
+
+From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+
+This encoder-only device is present four times on this SoC, and should
+support everything the rk3568 vepu supports (so JPEG, H.264 and VP8
+encoding). No fallback compatible has been added, since the operating
+systems might already support RK3568 VEPU and want to avoid registering
+four of them separately considering they can be used as a cluster.
+
+Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vepu.yaml
+@@ -17,6 +17,7 @@ properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-vepu
++ - rockchip,rk3588-vepu121
+
+ reg:
+ maxItems: 1
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:43 +0200
+Subject: media: dt-bindings: rockchip-vpu: Add RK3588 VPU121
+
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+
+RK3588 has four Hantro H1 VEPUs (encoder-only) modules and one combined
+Hantro H1/G1 VPU (decoder and encoder). These are not described as
+separate IP, since they are sharing an internal cache. This adds the
+RK3588 specific compatible string for the combined VPU, which seems to
+be identical to the version found in the RK3568.
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+index 111111111111..222222222222 100644
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -31,6 +31,9 @@ properties:
+ - items:
+ - const: rockchip,rk3228-vpu
+ - const: rockchip,rk3399-vpu
++ - items:
++ - const: rockchip,rk3588-vpu121
++ - const: rockchip,rk3568-vpu
+
+ reg:
+ maxItems: 1
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:44 +0200
+Subject: media: hantro: Disable multicore support
+
+Avoid exposing equal Hantro video codecs to userspace. Equal video
+codecs allow scheduling work between the cores. For that kernel support
+is required, which does not yet exist. Until that is implemented avoid
+exposing each core separately to userspace so that multicore can be
+added in the future without breaking userspace ABI.
+
+This was written with Rockchip RK3588 in mind (which has 4 Hantro H1
+cores), but applies to all SoCs.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/media/platform/verisilicon/hantro_drv.c | 37 ++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
++++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -992,6 +992,39 @@ static const struct media_device_ops hantro_m2m_media_ops = {
+ .req_queue = v4l2_m2m_request_queue,
+ };
+
++/*
++ * Some SoCs, like RK3588 have multiple identical Hantro cores, but the
++ * kernel is currently missing support for multi-core handling. Exposing
++ * separate devices for each core to userspace is bad, since that does
++ * not allow scheduling tasks properly (and creates ABI). With this workaround
++ * the driver will only probe for the first core and early exit for the other
++ * cores. Once the driver gains multi-core support, the same technique
++ * for detecting the main core can be used to cluster all cores together.
++ */
++static int hantro_disable_multicore(struct hantro_dev *vpu)
++{
++ const char *compatible;
++ struct device_node *node;
++ int ret;
++
++ /* Intentionally ignores the fallback strings */
++ ret = of_property_read_string(vpu->dev->of_node, "compatible", &compatible);
++ if (ret)
++ return ret;
++
++ /* first compatible node found from the root node is considered the main core */
++ node = of_find_compatible_node(NULL, NULL, compatible);
++ if (!node)
++ return -EINVAL; /* broken DT? */
++
++ if (vpu->dev->of_node != node) {
++ dev_info(vpu->dev, "missing multi-core support, ignoring this instance\n");
++ return -ENODEV;
++ }
++
++ return 0;
++}
++
+ static int hantro_probe(struct platform_device *pdev)
+ {
+ const struct of_device_id *match;
+@@ -1011,6 +1044,10 @@ static int hantro_probe(struct platform_device *pdev)
+ match = of_match_node(of_hantro_match, pdev->dev.of_node);
+ vpu->variant = match->data;
+
++ ret = hantro_disable_multicore(vpu);
++ if (ret)
++ return ret;
++
+ /*
+ * Support for nxp,imx8mq-vpu is kept for backwards compatibility
+ * but it's deprecated. Please update your DTS file to use
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:45 +0200
+Subject: media: hantro: Add RK3588 VEPU121
+
+RK3588 handling is exactly the same as RK3568. This is not
+handled using fallback compatibles to avoid exposing multiple
+video devices on kernels not having the multicore disable
+patch.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/media/platform/verisilicon/hantro_drv.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/platform/verisilicon/hantro_drv.c
++++ b/drivers/media/platform/verisilicon/hantro_drv.c
+@@ -722,6 +722,7 @@ static const struct of_device_id of_hantro_match[] = {
+ { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
+ { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
+ { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
++ { .compatible = "rockchip,rk3588-vepu121", .data = &rk3568_vpu_variant, },
+ { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
+ #endif
+ #ifdef CONFIG_VIDEO_HANTRO_IMX8M
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:46 +0200
+Subject: arm64: dts: rockchip: Add VEPU121 to RK3588
+
+From: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+
+RK3588 has 4 Hantro G1 encoder-only cores. They are all independent IP,
+but can be used as a cluster (i.e. sharing work between the cores).
+These cores are called VEPU121 in the TRM. The TRM describes one more
+VEPU121, but that is combined with a Hantro H1. That one will be handled
+using the VPU binding instead.
+
+Signed-off-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 80 ++++++++++
+ 1 file changed, 80 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1282,6 +1282,86 @@ power-domain@RK3588_PD_SDMMC {
+ };
+ };
+
++ vepu121_0: video-codec@fdba0000 {
++ compatible = "rockchip,rk3588-vepu121";
++ reg = <0x0 0xfdba0000 0x0 0x800>;
++ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vepu121_0_mmu>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ };
++
++ vepu121_0_mmu: iommu@fdba0800 {
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0xfdba0800 0x0 0x40>;
++ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
++ clock-names = "aclk", "iface";
++ power-domains = <&power RK3588_PD_VDPU>;
++ #iommu-cells = <0>;
++ };
++
++ vepu121_1: video-codec@fdba4000 {
++ compatible = "rockchip,rk3588-vepu121";
++ reg = <0x0 0xfdba4000 0x0 0x800>;
++ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vepu121_1_mmu>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ };
++
++ vepu121_1_mmu: iommu@fdba4800 {
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0xfdba4800 0x0 0x40>;
++ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
++ clock-names = "aclk", "iface";
++ power-domains = <&power RK3588_PD_VDPU>;
++ #iommu-cells = <0>;
++ };
++
++ vepu121_2: video-codec@fdba8000 {
++ compatible = "rockchip,rk3588-vepu121";
++ reg = <0x0 0xfdba8000 0x0 0x800>;
++ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vepu121_2_mmu>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ };
++
++ vepu121_2_mmu: iommu@fdba8800 {
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0xfdba8800 0x0 0x40>;
++ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
++ clock-names = "aclk", "iface";
++ power-domains = <&power RK3588_PD_VDPU>;
++ #iommu-cells = <0>;
++ };
++
++ vepu121_3: video-codec@fdbac000 {
++ compatible = "rockchip,rk3588-vepu121";
++ reg = <0x0 0xfdbac000 0x0 0x800>;
++ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vepu121_3_mmu>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ };
++
++ vepu121_3_mmu: iommu@fdbac800 {
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0xfdbac800 0x0 0x40>;
++ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
++ clock-names = "aclk", "iface";
++ power-domains = <&power RK3588_PD_VDPU>;
++ #iommu-cells = <0>;
++ };
++
+ av1d: video-codec@fdc70000 {
+ compatible = "rockchip,rk3588-av1-vpu";
+ reg = <0x0 0xfdc70000 0x0 0x800>;
+-- 
+Armbian
+
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 13 Jun 2024 15:48:47 +0200
+Subject: arm64: dts: rockchip: Add VPU121 support for RK3588
+
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+
+Enable Hantro G1 video decoder in RK3588's devicetree.
+
+Tested with FFmpeg v4l2_request code taken from [1]
+with MPEG2, H.264 and VP8 samples.
+
+[1] https://github.com/LibreELEC/LibreELEC.tv/blob/master/packages/multimedia/ffmpeg/patches/v4l2-request/ffmpeg-001-v4l2-request.patch
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Tested-by: Hugh Cole-Baker <sigmaris@gmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 ++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1282,6 +1282,27 @@ power-domain@RK3588_PD_SDMMC {
+ };
+ };
+
++ vpu121: video-codec@fdb50000 {
++ compatible = "rockchip,rk3588-vpu121", "rockchip,rk3568-vpu";
++ reg = <0x0 0xfdb50000 0x0 0x800>;
++ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
++ interrupt-names = "vdpu";
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ clock-names = "aclk", "hclk";
++ iommus = <&vpu121_mmu>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ };
++
++ vpu121_mmu: iommu@fdb50800 {
++ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0xfdb50800 0x0 0x40>;
++ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
++ clock-names = "aclk", "iface";
++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
++ power-domains = <&power RK3588_PD_VDPU>;
++ #iommu-cells = <0>;
++ };
++
+ vepu121_0: video-codec@fdba0000 {
+ compatible = "rockchip,rk3588-vepu121";
+ reg = <0x0 0xfdba0000 0x0 0x800>;
+-- 
+Armbian
+
@@ -14,7 +14,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
 index 111111111111..222222222222 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -1414,6 +1414,61 @@ i2s9_8ch: i2s@fddfc000 {
+@@ -1515,6 +1515,61 @@ i2s9_8ch: i2s@fddfc000 {
  status = "disabled";
  };
 

@@ -13,7 +13,7 @@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/roc
 index 111111111111..222222222222 100644
 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
-@@ -2883,6 +2883,7 @@ hdptxphy_hdmi0: phy@fed60000 {
+@@ -2984,6 +2984,7 @@ hdptxphy_hdmi0: phy@fed60000 {
  reg = <0x0 0xfed60000 0x0 0x2000>;
  clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
  clock-names = "ref", "apb";