Add rust package embedded-std
with module string
#3675
ci.yml
on: push
Build dependencies
2m 23s
Basic linting
17s
elastic-buffer-sim-topologies simulation matrix generation
20s
bittide-instances hardware-in-the-loop test matrix generation
15s
bittide-instances synthesis matrix generation
20s
Rust Lints
24s
Firmware Support Unit Tests
2m 53s
Host Tools Unit Tests
30s
Firmware Limit Checks
1m 45s
elastic-buffer-sim unittests
1m 45s
Bittide tests
1m 46s
bittide-instances doctests
1m 44s
bittide-instances unittests
1m 41s
Matrix: Simulate network
Matrix: synth
Matrix: HITL
All jobs finished
4s
Annotations
2 errors and 6 warnings
Rust Lints
Process completed with exit code 1.
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All jobs finished
Process completed with exit code 1.
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Bittide tests
Docker rm fail with exit code 1
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HITL (boardTestSimple, test, All)
No files were found with the provided path: _build/vivado/*/ila-data. No artifacts will be uploaded.
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HITL (fincFdecTests, test, Specific [-1])
No files were found with the provided path: _build/vivado/*/ila-data. No artifacts will be uploaded.
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HITL (syncInSyncOut, test, All)
No files were found with the provided path: _build/vivado/*/ila-data. No artifacts will be uploaded.
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HITL (transceiversUpTest, test, All)
No files were found with the provided path: _build/vivado/*/ila-data. No artifacts will be uploaded.
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HITL (vexRiscvTest, test, Specific [-1])
No files were found with the provided path: _build/vivado/*/ila-data. No artifacts will be uploaded.
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Artifacts
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Clock Control Reports
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_build-boardTestExtended
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7.85 MB |
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_build-boardTestExtended-debug
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355 KB |
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_build-boardTestSimple
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3.13 MB |
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_build-clockControlDemo0
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6.83 MB |
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_build-fincFdecTests
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4.78 MB |
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_build-fullMeshHwCcTest
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133 MB |
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_build-fullMeshHwCcTest-debug
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3.65 MB |
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_build-fullMeshSwCcTest
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163 MB |
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_build-fullMeshSwCcTest-debug
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3.55 MB |
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_build-syncInSyncOut
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3.35 MB |
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_build-transceiversUpTest
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15.9 MB |
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_build-vexRiscUartHello
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8.79 MB |
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_build-vexRiscvTest
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10.4 MB |
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gen-plots-hs-complete
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47.9 KB |
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