Add rust package `embedded-std` with module `string` #3675

Job	Run time
bittide-instances synthesis matrix generation	20s
bittide-instances hardware-in-the-loop test matrix generation	15s
Build dependencies	2m 23s
elastic-buffer-sim-topologies simulation matrix generation	20s
license-check	13s
License year check	20s
Basic linting	17s
elastic-buffer-sim unittests	1m 45s
Simulate network (complete, 16, 1000000, --nodes 2 --clock-offsets [-2,2] --frame-size 1500)	1m 46s
Bittide tests	1m 46s
Rust Lints	24s
bittide-instances doctests	1m 44s
Firmware Limit Checks	1m 45s
Firmware Support Unit Tests	2m 53s
Host Tools Unit Tests	30s
bittide-instances unittests	1m 41s
synth (clockControlDemo0, bitstream)	4m 26s
synth (vexRiscUartHello, bitstream)	4m 45s
synth (boardTestExtended, test, All)	5m 32s
synth (boardTestSimple, test, All)	4m 18s
synth (fincFdecTests, test, Specific [-1])	5m 47s
synth (fullMeshHwCcTest, test, All)	10m 29s
synth (fullMeshSwCcTest, test, All)	11m 10s
synth (syncInSyncOut, test, All)	4m 56s
synth (transceiversUpTest, test, All)	7m 13s
synth (vexRiscvTest, test, Specific [-1])	4m 49s
HITL (boardTestExtended, test, All)	1m 40s
HITL (boardTestSimple, test, All)	1m 23s
HITL (fincFdecTests, test, Specific [-1])	1m 9s
HITL (fullMeshHwCcTest, test, All)	3m 17s
HITL (fullMeshSwCcTest, test, All)	3m 20s
HITL (syncInSyncOut, test, All)	1m 23s
HITL (transceiversUpTest, test, All)	2m 22s
HITL (vexRiscvTest, test, Specific [-1])	1m 5s
Generate clock control simulation report	51s
All jobs finished	4s
	1h 38m 21s

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