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x64: improve multiplication lowering #2889

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merged 3 commits into from
May 14, 2021

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abrown
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@abrown abrown commented May 10, 2021

Since the lowering of imul complicated the other ALU operations it was
matched with and since future commits will alter the multiplication
lowering further, this change moves the imul lowering to its own match
block. Then, it improves the filetests and uses VPMULLQ as a lowering
for imul.i64x2 when the instruction is available.

@github-actions github-actions bot added cranelift Issues related to the Cranelift code generator cranelift:area:x64 Issues related to x64 codegen labels May 10, 2021
@abrown abrown force-pushed the inst-format-5 branch 2 times, most recently from d86db43 to c42fe4e Compare May 13, 2021 23:18
Since the lowering of `imul` complicated the other ALU operations it was
matched with and since future commits will alter the multiplication
lowering further, this change moves the `imul` lowering to its own match
block.
This adds the machinery to encode the VPMULLQ instruction which is
available in AVX512VL and AVX512DQ. When these feature sets are
available, we use this instruction instead of a lengthy 12-instruction
sequence.
@abrown abrown requested a review from cfallin May 13, 2021 23:19
@abrown abrown marked this pull request as ready for review May 13, 2021 23:24
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Looks great!

@abrown abrown merged commit e676589 into bytecodealliance:main May 14, 2021
@abrown abrown deleted the inst-format-5 branch May 14, 2021 03:14
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2 participants