x64: Lower SIMD requirement to SSE2 #6625
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All instructions in Cranelift now have lowerings for SSE2 as a baseline, even if they're not exactly the speediest things in the world. This enables lowering the baseline required for the SIMD proposal for WebAssembly to SSE2, the base features set of x86_64. Lots of tests were updated here to remove explicit `has_foo=false` annotations as they no longer have any effect. Additionally fuzzing has been updated to enable disabling `sse3` and `ssse3` which will help stress-test all previously-added lowerings.
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With @fitzgen's excellent idea of actually testing these on somewhat real hardware I ran the test suite through QEMU with (I don't have actual old hardware to test on myeslf) |
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This commit removes a setting for Cranelift which I've found a bit confusing historically and I think is no longer necessary. The setting is currently documented as enabling SIMD instructions, but that only sort of works for the x64 backend and none of the other backends look at it. Historically this was used to flag to Cranelift that a higher x64 baseline feature set is required for codegen but as of bytecodealliance#6625 that's no longer necessary. Otherwise it seems more Cranelift-like nowadays to say that vector instructions generate SIMD instructions where non-vector instructions probably don't, but may still depending on activated CPU features. In that sense I'm not sure if a dedicated `enable_simd` setting is still motivated, so this PR removes it. This renames some features in the x86 backend such as `use_avx_simd` to `use_avx` since the `_simd` part is no longer part of the computation now that `enable_simd` is gone.
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This commit removes a setting for Cranelift which I've found a bit confusing historically and I think is no longer necessary. The setting is currently documented as enabling SIMD instructions, but that only sort of works for the x64 backend and none of the other backends look at it. Historically this was used to flag to Cranelift that a higher x64 baseline feature set is required for codegen but as of #6625 that's no longer necessary. Otherwise it seems more Cranelift-like nowadays to say that vector instructions generate SIMD instructions where non-vector instructions probably don't, but may still depending on activated CPU features. In that sense I'm not sure if a dedicated `enable_simd` setting is still motivated, so this PR removes it. This renames some features in the x86 backend such as `use_avx_simd` to `use_avx` since the `_simd` part is no longer part of the computation now that `enable_simd` is gone.
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All instructions in Cranelift now have lowerings for SSE2 as a baseline, even if they're not exactly the speediest things in the world. This enables lowering the baseline required for the SIMD proposal for WebAssembly to SSE2, the base features set of x86_64. Lots of tests were updated here to remove explicit
has_foo=falseannotations as they no longer have any effect.Additionally fuzzing has been updated to enable disabling
sse3andssse3which will help stress-test all previously-added lowerings.