Merge resource sharing and minimize regs #444
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…e-regs and resource-sharing. fixes #442
* Give @external semantics for verilog backend @external(1) on a memory makes the backend generate code to initialize memories and dump out their final states. Every other memory is ignored. Fud is stricter about what memories it expects in the inputs and outputs. * fmt * relay memories are external * fmt * line nonsense * more reformat * more test fixing * Tests * Commas are the worst * undo change to pow test Co-authored-by: cgyurgyik <gyurgyikcp@gmail.com>
* remove std_ prefix from math library * update test * update relay impl * Add prefix and suffix to Relay components. * Add arity only. * Remove re. Co-authored-by: Chris Gyurgyik <37983775+cgyurgyik@users.noreply.github.com> Co-authored-by: cgyurgyik <gyurgyikcp@gmail.com>
* Test Language Tutorial examples * update doc link * add data.json * link to calyx files
* Tutorial for memory by reference. * Update english * runt * Use mod output. * Update Summary. * rename. * Fix test.
* added check to ensure literal values are representable in the given bitwidth * added a few tests * fix edge case * fix my formatting crimes * appease clippy * formatting, again
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