Add TriCore Architecture

.gitignore

@@ -62,6 +62,7 @@ tests/test_skipdata
 tests/test_sparc
 tests/test_systemz
 tests/test_xcore
+tests/test_tricore
 tests/*.static
 tests/test_customized_mnem
 tests/test_m68k

CMakeLists.txt

@@ -39,13 +39,14 @@ option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS}
 option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
 option(CAPSTONE_BUILD_TESTS "Build tests" ${PROJECT_IS_TOP_LEVEL})
 option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL})
+option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF)
 option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
 option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON)
 option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
 option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
 
-set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH)
-set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH)
+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore)
 
 list(LENGTH SUPPORTED_ARCHITECTURES count)
 math(EXPR count "${count}-1")
@@ -135,6 +136,7 @@ set(HEADERS_COMMON
     include/capstone/bpf.h
     include/capstone/riscv.h
     include/capstone/sh.h
+    include/capstone/tricore.h
     include/capstone/platform.h
 )
 
@@ -533,7 +535,28 @@ if(CAPSTONE_SH_SUPPORT)
     set(TEST_SOURCES ${TEST_SOURCES} test_sh.c)
 endif()
 
-if(CAPSTONE_OSXKERNEL_SUPPORT)
+if (CAPSTONE_TRICORE_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_TRICORE)
+    set(SOURCES_TRICORE
+            arch/TriCore/TriCoreDisassembler.c
+            arch/TriCore/TriCoreInstPrinter.c
+            arch/TriCore/TriCoreMapping.c
+            arch/TriCore/TriCoreModule.c
+            )
+    set(HEADERS_TRICORE
+            arch/TriCore/TriCoreDisassembler.h
+            arch/TriCore/TriCoreGenAsmWriter.inc
+            arch/TriCore/TriCoreGenDisassemblerTables.inc
+            arch/TriCore/TriCoreGenInstrInfo.inc
+            arch/TriCore/TriCoreGenRegisterInfo.inc
+            arch/TriCore/TriCoreInstPrinter.h
+            arch/TriCore/TriCoreMapping.h
+            arch/TriCore/TriCoreModule.h
+            )
+    set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c)
+endif ()
+
+if (CAPSTONE_OSXKERNEL_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif()
 
@@ -556,6 +579,7 @@ set(ALL_SOURCES
     ${SOURCES_BPF}
     ${SOURCES_RISCV}
     ${SOURCES_SH}
+    ${SOURCES_TRICORE}
 )
 
 set(ALL_HEADERS
@@ -578,6 +602,7 @@ set(ALL_HEADERS
     ${HEADERS_BPF}
     ${HEADERS_RISCV}
     ${HEADERS_SH}
+    ${HEADERS_TRICORE}
 )
 
 ## properties
@@ -640,6 +665,7 @@ source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
 source_group("Source\\BPF" FILES ${SOURCES_BPF})
 source_group("Source\\RISCV" FILES ${SOURCES_RISCV})
 source_group("Source\\SH" FILES ${SOURCES_SH})
+source_group("Source\\TriCore" FILES ${SOURCES_TRICORE})
 
 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@@ -660,6 +686,7 @@ source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
 source_group("Include\\BPF" FILES ${HEADERS_BPF})
 source_group("Include\\RISCV" FILES ${HEADERS_RISCV})
 source_group("Include\\SH" FILES ${HEADERS_SH})
+source_group("Include\\TriCore" FILES ${HEADERS_TRICORE})
 
 ## installation
 if(CAPSTONE_INSTALL)
@@ -726,3 +753,20 @@ if(CAPSTONE_BUILD_CSTOOL)
         install(TARGETS cstool EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
     endif()
 endif()
+
+if(CAPSTONE_BUILD_CSTEST)
+    find_package(CMOCKA)
+
+    file(GLOB CSTEST_SRC suite/cstest/src/*.c)
+    add_executable(cstest ${CSTEST_SRC})
+    target_link_libraries(cstest PUBLIC capstone ${CMOCKA_LIBRARIES})
+    target_include_directories(cstest PRIVATE
+            $<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
+            ${PROJECT_SOURCE_DIR}/suite/cstest/include
+            ${CMOCKA_INCLUDE_DIR}
+            )
+
+    if(CAPSTONE_INSTALL)
+        install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
+    endif()
+endif()

COMPILE.TXT

@@ -100,6 +100,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 	/usr/include/capstone/wasm.h
 	/usr/include/capstone/x86.h
 	/usr/include/capstone/xcore.h
+	/usr/include/capstone/tricore.h
 	/usr/lib/libcapstone.a
 	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
 

COMPILE_CMAKE.TXT

@@ -29,6 +29,7 @@ Get CMake for free from http://www.cmake.org.
   - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
   - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
   - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
+  - CAPSTONE_TRICORE_SUPPORT: support TriCore. Run cmake with -DCAPSTONE_TRICORE_SUPPORT=0 to remove TriCore.
   - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
   - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
   - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.

COMPILE_MSVC.TXT

@@ -39,6 +39,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
   - CAPSTONE_HAS_SYSZ: support SystemZ. Delete this to remove SystemZ support.
   - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
   - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.
+  - CAPSTONE_HAS_TRICORE: support TriCore. Delete this to remove TriCore support.
 
   By default, all 9 architectures are compiled in.
 

CREDITS.TXT

@@ -87,3 +87,4 @@ david942j: BPF (both classic and extended) architecture.
 fanfuqiang & citypw & porto703 : RISCV architecture.
 Josh "blacktop" Maine: Arm64 architecture improvements.
 Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
+Billow & Sidneyp : TriCore architecture.

HACK.TXT

@@ -14,11 +14,13 @@ Capstone source is organized as followings.
 │   ├── Mips        <- Mips engine
 │   ├── MOS65XX     <- MOS65XX engine
 │   ├── PowerPC     <- PowerPC engine
+│   ├── RISCV       <- RISCV engine
+│   ├── SH          <- SH engine
 │   ├── Sparc       <- Sparc engine
 │   ├── SystemZ     <- SystemZ engine
 │   ├── TMS320C64x  <- TMS320C64x engine
-│   ├── X86         <- X86 engine
-│   └── XCore       <- XCore engine
+│   ├── TriCore     <- TriCore engine
+│   └── WASM        <- WASM engine
 ├── bindings        <- all bindings are under this dir
 │   ├── java        <- Java bindings + test code
 │   ├── ocaml       <- Ocaml bindings + test code
@@ -85,7 +87,7 @@ Tests:
 - tests/test_detail.c
 - tests/test_iter.c
 - tests/test_newarch.c
-- suite/fuzz/fuzz_disasm.c: add the architecture and its modes to the list of fuzzed platforms
+- suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms
 - suite/capstone_get_setup.c
 - suite/MC/newarch/mode.mc: samples
 - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing

MCInstrDesc.h

@@ -57,7 +57,11 @@ enum MCOI_OperandType {
 	MCOI_OPERAND_GENERIC_5 = 11,
 	MCOI_OPERAND_LAST_GENERIC = 11,
 
-	MCOI_OPERAND_FIRST_TARGET = 12,
+	MCOI_OPERAND_FIRST_GENERIC_IMM = 12,
+	MCOI_OPERAND_GENERIC_IMM_0 = 12,
+	MCOI_OPERAND_LAST_GENERIC_IMM = 12,
+
+	MCOI_OPERAND_FIRST_TARGET = 13,
 };
 
 

Makefile

@@ -314,11 +314,22 @@ ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
 	LIBOBJ_BPF += $(LIBSRC_BPF:%.c=$(OBJDIR)/%.o)
 endif
 
+DEP_TRICORE =
+DEP_TRICORE +=$(wildcard arch/TriCore/TriCore*.inc)
+
+LIBOBJ_TRICORE =
+ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_TRICORE
+	LIBSRC_TRICORE += $(wildcard arch/TriCore/TriCore*.c)
+	LIBOBJ_TRICORE += $(LIBSRC_TRICORE:%.c=$(OBJDIR)/%.o)
+endif
+
 
 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
 LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
 LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
+LIBOBJ += $(LIBOBJ_TRICORE)
 LIBOBJ += $(OBJDIR)/MCInst.o
 
 
@@ -454,6 +465,7 @@ $(LIBOBJ_RISCV): $(DEP_RISCV)
 $(LIBOBJ_WASM): $(DEP_WASM)
 $(LIBOBJ_MOS65XX): $(DEP_MOS65XX)
 $(LIBOBJ_BPF): $(DEP_BPF)
+$(LIBOBJ_TRICORE): $(DEP_TRICORE)
 
 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
@@ -539,7 +551,7 @@ dist:
 	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
-TESTS  = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc	
+TESTS  = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc test_tricore
 TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf
 TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
 TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static

README.md

@@ -16,7 +16,7 @@ Capstone offers some unparalleled features:
 
 - Support multiple hardware architectures: ARM, ARM64 (ARMv8), BPF, Ethereum VM,
   M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ,
-  TMS320C64X, Webassembly, XCore and X86 (16, 32, 64).
+  TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64).
 
 - Having clean/simple/lightweight/intuitive architecture-neutral API.
 

arch/TriCore/TriCore.td

@@ -0,0 +1,134 @@
+//===-- TriCore.td - Describe the TriCore Target Machine ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This is the top level entry point for the TriCore target.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces which we are implementing
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// Descriptions
+//===----------------------------------------------------------------------===//
+
+// Specify whether target support specific TRICORE ISA variants.
+
+def HasV110Ops   : SubtargetFeature<"v1.1", "HasV110Ops", "true",
+								   "Support TriCore v1.1 instructions",
+								   []>;
+def HasV120Ops   : SubtargetFeature<"v1.2", "HasV120Ops", "true",
+								   "Support TriCore v1.2 instructions",
+								   []>;
+def HasV130Ops   : SubtargetFeature<"v1.3", "HasV130Ops", "true",
+								   "Support TriCore v1.3 instructions",
+								   []>;
+def HasV131Ops   : SubtargetFeature<"v1.3.1", "HasV131Ops", "true",
+								   "Support TriCore v1.3.1 instructions",
+								   []>;
+def HasV160Ops   : SubtargetFeature<"v1.6", "HasV160Ops", "true",
+								   "Support TriCore v1.6 instructions",
+								   []>;
+def HasV161Ops   : SubtargetFeature<"v1.6.1", "HasV161Ops", "true",
+								   "Support TriCore v1.6.1 instructions",
+								   []>;
+def HasV162Ops   : SubtargetFeature<"v1.6.2", "HasV162Ops", "true",
+								   "Support TriCore v1.6.2 instructions",
+								   []>;
+
+def HasV110     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV110Ops), "v1.1">;
+def HasV120     : Predicate<"HasV120Ops()">, AssemblerPredicate<(all_of HasV120Ops), "v1.2">;
+def HasV130     : Predicate<"HasV130Ops()">, AssemblerPredicate<(all_of HasV130Ops), "v1.3">;
+def HasV131     : Predicate<"HasV131Ops()">, AssemblerPredicate<(all_of HasV131Ops), "v1.3.1">;
+def HasV160     : Predicate<"HasV160Ops()">, AssemblerPredicate<(all_of HasV160Ops), "v1.6">;
+def HasV161     : Predicate<"HasV161Ops()">, AssemblerPredicate<(all_of HasV161Ops), "v1.6.1">;
+def HasV162     : Predicate<"HasV162Ops()">, AssemblerPredicate<(all_of HasV162Ops), "v1.6.2">;
+
+def HasV120_UP  : Predicate<"HasV120Ops() || HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV120Ops, HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v120up">;
+def HasV130_UP  : Predicate<"HasV130Ops() || HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV130Ops, HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v130up">;
+def HasV131_UP  : Predicate<"HasV131Ops() || HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV131Ops, HasV160Ops, HasV161Ops, HasV162Ops), "v131up">;
+def HasV160_UP  : Predicate<"HasV160Ops() || HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV160Ops, HasV161Ops, HasV162Ops), "v160up">;
+def HasV161_UP  : Predicate<"HasV161Ops() || HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV161Ops, HasV162Ops), "v161up">;
+def HasV162_UP  : Predicate<"HasV162Ops()">
+				, AssemblerPredicate<(any_of HasV162Ops), "v162up">;
+
+def HasV120_DN : Predicate<"HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV120Ops, HasV110Ops), "v120dn">;
+def HasV130_DN : Predicate<"HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV130Ops, HasV120Ops, HasV110Ops), "v130dn">;
+def HasV131_DN : Predicate<"HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v131dn">;
+def HasV160_DN : Predicate<"HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v160dn">;
+def HasV161_DN : Predicate<"HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v161dn">;
+def HasV162_DN : Predicate<"HasV162Ops() || HasV161Ops() || HasV160Ops() || HasV131Ops() || HasV130Ops() || HasV120Ops() || HasV110Ops()">,
+				AssemblerPredicate<(any_of HasV162Ops, HasV161Ops, HasV160Ops, HasV131Ops, HasV130Ops, HasV120Ops, HasV110Ops), "v162dn">;
+
+
+class Architecture<string fname, string aname, list<SubtargetFeature> features = []>
+  : SubtargetFeature<fname, "TriCoreArch", aname,
+					 !strconcat(aname, " architecture"), features>;
+
+class ProcNoItin<string Name, list<SubtargetFeature> Features>
+  : Processor<Name, NoItineraries, Features>;
+
+
+def TRICORE_V1_1    : Architecture<"tricore-v1.1",    "TRICOREv110", [HasV110Ops]>;
+def TRICORE_V1_2    : Architecture<"tricore-V1.2",    "TRICOREv120", [HasV120Ops]>;
+def TRICORE_V1_3    : Architecture<"tricore-V1.3",    "TRICOREv130", [HasV130Ops]>;
+def TRICORE_V1_3_1  : Architecture<"tricore-V1.3.1",  "TRICOREv131", [HasV131Ops]>;
+def TRICORE_V1_6    : Architecture<"tricore-V1.6",    "TRICOREv160", [HasV160Ops]>;
+def TRICORE_V1_6_1  : Architecture<"tricore-V1.6.1",  "TRICOREv161", [HasV161Ops]>;
+def TRICORE_V1_6_2  : Architecture<"tricore-V1.6.2",  "TRICOREv162", [HasV162Ops]>;
+def TRICORE_PCP     : Architecture<"tricore-PCP",     "TRICOREpcp">;
+def TRICORE_PCP2    : Architecture<"tricore-PCP2",    "TRICOREpcp2">;
+
+def TRICORE_RIDER_A : Architecture<"tricore-rider-a", "TRICOREv110", [TRICORE_V1_1]>;
+
+
+include "TriCoreRegisterInfo.td"
+include "TriCoreInstrInfo.td"
+include "TriCoreCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// TriCore processors supported.
+//===----------------------------------------------------------------------===//
+
+def : ProcNoItin<"tc1796",  [TRICORE_V1_3]>;
+def : ProcNoItin<"tc1797",  [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc27x",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc161",   [TRICORE_V1_6_1]>;
+def : ProcNoItin<"tc162",   [TRICORE_V1_6_2]>;
+def : ProcNoItin<"tc16",    [TRICORE_V1_6]>;
+def : ProcNoItin<"tc131",   [TRICORE_V1_3_1]>;
+def : ProcNoItin<"tc13",    [TRICORE_V1_3]>;
+
+def TriCoreAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
+def TriCoreInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// Declare the target which we are implementing
+//===----------------------------------------------------------------------===//
+
+def TriCore : Target {
+  let InstructionSet = TriCoreInstrInfo;
+  let AssemblyWriters = [TriCoreAsmWriter];
+}