tidy

chipsalliance · Oct 19, 2023 · 7f5b18c · 7f5b18c
1 parent 1430408
commit 7f5b18c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/DesignCompile/NetlistElaboration.cpp b/src/DesignCompile/NetlistElaboration.cpp
@@ -1181,7 +1181,7 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) {
                   ports->push_back(p);
                   p->VpiName(formalName);
                   fC->populateCoreMembers(formalId, formalId, p);
-                  if (allSignalsConst.size()) {
+                  if (!allSignalsConst.empty()) {
                     auto found = allSignalsConst.find(p->VpiName());
                     if (found == allSignalsConst.end()) {
                       SymbolTable* symbols =
@@ -1218,7 +1218,7 @@ bool NetlistElaboration::high_conn_(ModuleInstance* instance) {
                        VObjectType::paExpression) {  // .p(s) connection by name
               sigId = tmp;
               Expression = tmp;
-              if (allSignalsConst.size()) {
+              if (!allSignalsConst.empty()) {
                 auto found = allSignalsConst.find(formalName);
                 if (found == allSignalsConst.end()) {
                   SymbolTable* symbols =