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Optional pp location in syntax error messages #3985

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Sep 22, 2024
Merged

Optional pp location in syntax error messages #3985

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3 changes: 3 additions & 0 deletions include/Surelog/CommandLine/CommandLineParser.h
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Expand Up @@ -97,6 +97,8 @@ class CommandLineParser final {
PathId getCacheDirId() const { return m_cacheDirId; }
PathId getPrecompiledDirId() const { return m_precompiledDirId; }
bool usePPOutputFileLocation() const { return m_ppOutputFileLocation; }
void printExtraPpLineInfo(bool on) { m_ppPrintLineInfo = on; }
bool printExtraPpLineInfo() { return m_ppPrintLineInfo; }
/* PP Output content generation options */
bool filterFileLine() const { return m_filterFileLine; }
void setFilterFileLine(bool val) { m_filterFileLine = val; }
Expand Down Expand Up @@ -345,6 +347,7 @@ class CommandLineParser final {
bool m_profile;
bool m_parseBuiltIn;
bool m_ppOutputFileLocation;
bool m_ppPrintLineInfo;
PathId m_programId;
std::string m_exeCommand;
std::set<std::string, std::less<>> m_topLevelModules;
Expand Down
6 changes: 4 additions & 2 deletions include/Surelog/SourceCompile/AntlrParserErrorListener.h
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Expand Up @@ -38,13 +38,14 @@ class ParseFile;
class AntlrParserErrorListener : public antlr4::ANTLRErrorListener {
public:
AntlrParserErrorListener(ParseFile *parser, bool watchDogOn,
uint32_t lineOffset, PathId fileId)
uint32_t lineOffset, PathId fileId, bool printExtraPpLineInfo)
: m_parser(parser),
m_reportedSyntaxError(0),
m_watchDogOn(watchDogOn),
m_barked(false),
m_lineOffset(lineOffset),
m_fileId(fileId) {}
m_fileId(fileId),
m_printExtraPpLineInfo(printExtraPpLineInfo) {}

~AntlrParserErrorListener() override{};

Expand Down Expand Up @@ -76,6 +77,7 @@ class AntlrParserErrorListener : public antlr4::ANTLRErrorListener {
uint32_t m_lineOffset;
PathId m_fileId;
std::vector<std::string> m_fileContent;
bool m_printExtraPpLineInfo;
};

}; // namespace SURELOG
Expand Down
4 changes: 4 additions & 0 deletions src/CommandLine/CommandLineParser.cpp
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Expand Up @@ -226,6 +226,7 @@ static const std::initializer_list<std::string_view> helpText = {
" output",
" -pploc Output message location in terms of post",
" preprocessor location",
" -ppextra_loc Adds pre-processor location to syntax errors"
" -noinfo Filters out INFO messages",
" -nonote Filters out NOTE messages",
" -nowarning Filters out WARNING messages",
Expand Down Expand Up @@ -393,6 +394,7 @@ CommandLineParser::CommandLineParser(ErrorContainer* errors,
m_profile(false),
m_parseBuiltIn(true),
m_ppOutputFileLocation(false),
m_ppPrintLineInfo(false),
m_sverilog(false),
m_dumpUhdm(false),
m_elabUhdm(false),
Expand Down Expand Up @@ -1311,6 +1313,8 @@ bool CommandLineParser::parseCommandLine(int32_t argc, const char** argv) {
m_elabUhdm = true;
} else if (all_arguments[i] == "-pploc") {
m_ppOutputFileLocation = true;
} else if (all_arguments[i] == "-ppextra_loc") {
m_ppPrintLineInfo = true;
} else if (all_arguments[i] == "-pythonlistener") {
m_writePpOutput = true;
m_parse = true;
Expand Down
7 changes: 5 additions & 2 deletions src/SourceCompile/AntlrParserErrorListener.cpp
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Expand Up @@ -47,8 +47,11 @@ void AntlrParserErrorListener::syntaxError(
if (!lineText.empty()) {
lineText.push_back('\n');
lineText.append(charPositionInLine, ' ');
StrAppend(&lineText, "^-- ", fileSystem->toPath(m_fileId), ":", line, ":",
charPositionInLine, ":");
if (m_printExtraPpLineInfo)
StrAppend(&lineText, "^-- ", fileSystem->toPath(m_fileId), ":", line,
":", charPositionInLine, ":");
else
StrAppend(&lineText, "^--");
}
}
if (m_reportedSyntaxError < 10) {
Expand Down
4 changes: 2 additions & 2 deletions src/SourceCompile/ParseFile.cpp
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Expand Up @@ -287,8 +287,8 @@ bool ParseFile::parseOneFile_(PathId fileId, uint32_t lineOffset) {
new antlr4::ANTLRInputStream(m_sourceText);
}

m_antlrParserHandler->m_errorListener =
new AntlrParserErrorListener(this, false, lineOffset, fileId);
m_antlrParserHandler->m_errorListener = new AntlrParserErrorListener(
this, false, lineOffset, fileId, clp->printExtraPpLineInfo());
m_antlrParserHandler->m_lexer =
new SV3_1aLexer(m_antlrParserHandler->m_inputStream);
VerilogVersion version = VerilogVersion::SystemVerilog;
Expand Down
2 changes: 1 addition & 1 deletion tests/DiffSimpleIncludeAndMacros/DiffSimpleIncludeAndMacros.log
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Expand Up @@ -2,7 +2,7 @@
| | FILE UNIT COMP | ALL COMPILATION |
|-------|------------------|-------------------|
| FATAL | 0 | 0 |
|SYNTAX | 6 | 6 |
|SYNTAX | 3 | 3 |
| ERROR | 23 | 23 |
|WARNING| 12 | 12 |
| INFO | | |
Expand Down
2 changes: 1 addition & 1 deletion tests/ParamFile/ParamFileMacro.log
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Expand Up @@ -213,7 +213,7 @@ n<> u<206> t<Top_level_rule> c<1> l<3:1> el<32:1>
AST_DEBUG_END
[SNT:PA0207] ${SURELOG_DIR}/tests/ParamFile/dut.sv:4:28: Syntax error: extraneous input '/' expecting {''b0', ''b1', ''B0', ''B1', ''0', ''1', '1'b0', '1'b1', '1'bx', '1'bX', '1'B0', '1'B1', '1'Bx', '1'BX', Integral_number, Real_number, String, '(', 'virtual', 'type', 'const', 'local', 'super', '{', 'enum', 'struct', 'union', 'string', 'chandle', 'event', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'signed', 'unsigned', '$', '+', '-', DOLLAR_UNIT, '!', ''', 'this', DOLLAR_ROOT, 'randomize', 'sample', '&', '|', '~|', '~&', '^~', Escaped_identifier, '~', '^', '~^', Simple_identifier},
parameter SRAMInitFile = /toto/blah;
^-- ${SURELOG_DIR}/build/regression/ParamFileMacro/slpp_unit/lib/work/dut.sv:4:28:.
^--.
[ FATAL] : 0
[ SYNTAX] : 1
[ ERROR] : 0
Expand Down
24 changes: 9 additions & 15 deletions tests/PreProcMacro/PreProcMacro.log
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Expand Up @@ -218,38 +218,32 @@ n<> u<210> t<Top_level_rule> c<1> l<14:1> el<24:1>
AST_DEBUG_END
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! A
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! A
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:17:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'A \n "A is ifdef'd"',
"A is ifdef'd"
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:18:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"A is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
"A is not ifdef'd"
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:20:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! B
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! B
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:26:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:6:4: Syntax error: no viable alternative at input 'B \n "B is ifdef'd"',
"B is ifdef'd"
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:27:4:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:8:4: Syntax error: extraneous input '"B is not ifdef'd"' expecting {';', 'default', 'module', 'endmodule', 'extern', 'macromodule', 'interface', 'program', 'virtual', 'class', 'timeunit', 'timeprecision', 'checker', 'type', 'clocking', 'defparam', 'bind', 'const', 'function', 'static', 'constraint', 'if', 'automatic', 'localparam', 'parameter', 'specparam', 'import', 'genvar', 'typedef', 'enum', 'struct', 'union', 'string', 'chandle', 'event', '[', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'bit', 'logic', 'reg', 'shortreal', 'real', 'realtime', 'supply0', 'supply1', 'tri', 'triand', 'trior', 'tri0', 'tri1', 'wire', 'uwire', 'wand', 'wor', 'trireg', 'signed', 'unsigned', 'interconnect', 'var', '$', 'export', DOLLAR_UNIT, '(*', 'assert', 'property', 'assume', 'cover', 'not', 'or', 'and', 'sequence', 'covergroup', 'pulldown', 'pullup', 'cmos', 'rcmos', 'bufif0', 'bufif1', 'notif0', 'notif1', 'nmos', 'pmos', 'rnmos', 'rpmos', 'nand', 'nor', 'xor', 'xnor', 'buf', 'tranif0', 'tranif1', 'rtranif1', 'rtranif0', 'tran', 'rtran', 'generate', 'case', 'for', 'global', 'initial', 'assign', 'alias', 'always', 'always_comb', 'always_latch', 'always_ff', 'restrict', 'let', 'this', 'randomize', 'final', 'task', 'specify', 'sample', '=', 'nettype', Escaped_identifier, Simple_identifier, '`pragma', SURELOG_MACRO_NOT_DEFINED},
"B is not ifdef'd"
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:29:4:.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '$display( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! A
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:.
[SNT:PA0207] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5:4: Syntax error: no viable alternative at input '( \n SURELOG_MACRO_NOT_DEFINED:check1!!!',
SURELOG_MACRO_NOT_DEFINED:check1!!! A
^-- ${SURELOG_DIR}/build/regression/PreProcMacro/slpp_all/lib/work/dut.sv:35:4:.
^--.
[ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:5: Unknown macro "check1".
[ERR:PA0203] ${SURELOG_DIR}/tests/PreProcMacro/dut.sv:7: Unknown macro "check2".
[ FATAL] : 0
[ SYNTAX] : 10
[ SYNTAX] : 8
[ ERROR] : 4
[WARNING] : 0
[ NOTE] : 0
2 changes: 1 addition & 1 deletion tests/PreprocLine/PreprocLine.log
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Expand Up @@ -79,7 +79,7 @@ n<> u<69> t<Top_level_rule> c<1> l<1:1> el<13:1>
AST_DEBUG_END
[SNT:PA0207] ${SURELOG_DIR}/tests/PreprocLine/fake.v:7: Syntax error: extraneous input '"line.vh"' expecting {Pound_Pound_delay, Pound_delay, ATSTAR, AT_PARENS_STAR, ';', 'type', 'local', 'super', '{', '->', 'if', 'foreach', 'byte', 'shortint', 'int', 'longint', 'integer', 'time', 'void', '$', '++', '--', DOLLAR_UNIT, '(*', 'assert', 'assume', 'cover', 'expect', 'disable', '##', '#', 'begin', 'end', 'case', 'for', 'assign', 'deassign', 'force', 'release', 'fork', 'repeat', '@', 'return', 'break', 'continue', 'wait', 'wait_order', 'unique', 'unique0', 'priority', 'casez', 'casex', 'randcase', 'forever', 'while', 'do', 'restrict', ''', 'randsequence', 'this', DOLLAR_ROOT, 'randomize', 'sample', '->>', Escaped_identifier, Simple_identifier, SURELOG_MACRO_NOT_DEFINED},
"line.vh"
^-- ${SURELOG_DIR}/build/regression/PreprocLine/slpp_all/lib/work/dut.sv:7:0:.
^--.
[ FATAL] : 0
[ SYNTAX] : 2
[ ERROR] : 1
Expand Down
15 changes: 3 additions & 12 deletions tests/SimpleIncludeAndMacros/SimpleIncludeAndMacros.log
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Expand Up @@ -92,21 +92,12 @@ ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:21:9: macro definition takes
${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_4.v:34: macro instance.
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top.v:69:0:.
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_1.v:69:0:.
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_2.v:69:0:.
^--.
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v:5: Syntax error: mismatched input '1' expecting <EOF>,
1 + 1 + 42 + 100 + c
^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_3.v:5:0:.
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/SimpleIncludeAndMacros/slpp_all/lib/work/SimpleIncludeAndMacros/top_4.v:69:0:.
^--.
[ FATAL] : 0
[ SYNTAX] : 6
[ SYNTAX] : 3
[ ERROR] : 23
[WARNING] : 12
[ NOTE] : 16
15 changes: 3 additions & 12 deletions tests/SimpleIncludeAndMacros/UnitSimpleIncludeAndMacros.log
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Expand Up @@ -85,26 +85,17 @@ ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:21:9: macro definition takes
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top.v".
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top.v:69:0:.
^--.
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_1.v".
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_1.v:69:0:.
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_2.v".
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_2.v:69:0:.
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v".
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_3.v:5: Syntax error: mismatched input '1' expecting <EOF>,
1 + 1 + 42 + 100 + c
^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_3.v:5:0:.
^--.
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/top_4.v".
[SNT:PA0207] ${SURELOG_DIR}/tests/SimpleIncludeAndMacros/mode.vh:26: Syntax error: mismatched input 'initial' expecting <EOF>,
initial $display("start", "msg1" , "msg2", "end");
^-- ${SURELOG_DIR}/build/regression/UnitSimpleIncludeAndMacros/slpp_unit/lib/work/SimpleIncludeAndMacros/top_4.v:69:0:.
[INF:PA0201] Parsing source file "${SURELOG_DIR}/tests/SimpleIncludeAndMacros/lib.v".
[ FATAL] : 0
[ SYNTAX] : 6
[ SYNTAX] : 3
[ ERROR] : 23
[WARNING] : 12
[ NOTE] : 6
2 changes: 1 addition & 1 deletion tests/TestMacros/TestMacros.log
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Expand Up @@ -5,7 +5,7 @@
[ERR:PP0111] ${SURELOG_DIR}/tests/TestMacros/TestMacros.v:12: Illegally redefining compiler directive "`define" as a macro name.
[SNT:PA0207] ${SURELOG_DIR}/tests/TestMacros/macros.inc:11:3: Syntax error: mismatched input 'begin' expecting <EOF>,
begin
^-- ${SURELOG_DIR}/build/regression/TestMacros/slpp_all/lib/work/TestMacros/TestMacros.v:3:3:.
^--.
[ FATAL] : 0
[ SYNTAX] : 2
[ ERROR] : 1
Expand Down
4 changes: 2 additions & 2 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
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Expand Up @@ -66,8 +66,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
[ 6%] Generating 10_lsu_bus_intf.sv
[ 12%] Generating 11_ifu_bp_ctl.sv
[ 18%] Generating 13_ifu_mem_ctl.sv
[ 25%] Generating 12_beh_lib.sv
[ 18%] Generating 12_beh_lib.sv
[ 25%] Generating 13_ifu_mem_ctl.sv
[ 31%] Generating 14_mem_lib.sv
[ 37%] Generating 15_exu.sv
[ 43%] Generating 16_dec_decode_ctl.sv
Expand Down
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