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Promote attr on net to array_nets #3995

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merged 1 commit into from
Oct 5, 2024
+13 −12
Merged

Promote attr on net to array_nets #3995

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5 changes: 3 additions & 2 deletions src/DesignCompile/NetlistElaboration.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2261,11 +2261,11 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
array_nets = s.MakeArray_netVec();
netlist->array_nets(array_nets);
}

array_nets->push_back(array_net);
obj->VpiParent(array_net);
UHDM::VectorOfnet* array_n = array_net->Nets();
array_n->push_back((net*)obj);
array_net->Attributes(((net*)obj)->Attributes());
} else {
if (nets == nullptr) {
nets = s.MakeNetVec();
Expand Down Expand Up @@ -2322,11 +2322,11 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
array_nets = s.MakeArray_netVec();
netlist->array_nets(array_nets);
}

array_nets->push_back(array_net);
obj->VpiParent(array_net);
UHDM::VectorOfnet* array_n = array_net->Nets();
array_n->push_back((net*)obj);
array_net->Attributes(((net*)obj)->Attributes());
} else {
if (nets == nullptr) {
nets = s.MakeNetVec();
Expand Down Expand Up @@ -2374,6 +2374,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
UHDM::VectorOfnet* array_n = array_net->Nets();
array_n->push_back(logicn);
obj = array_net;
array_net->Attributes(((net*)logicn)->Attributes());
} else {
logicn->VpiName(signame);
logicn->VpiSigned(sig->isSigned());
Expand Down
20 changes: 10 additions & 10 deletions third_party/tests/CoresSweRVMP/CoresSweRVMP.log
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Original file line number Diff line number Diff line change
Expand Up @@ -64,19 +64,19 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess;
-- Configuring done
-- Generating done
-- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess
[ 6%] Generating 11_ifu_bp_ctl.sv
[ 12%] Generating 12_beh_lib.sv
[ 18%] Generating 10_lsu_bus_intf.sv
[ 25%] Generating 13_ifu_mem_ctl.sv
[ 31%] Generating 14_mem_lib.sv
[ 37%] Generating 16_dec_decode_ctl.sv
[ 43%] Generating 15_exu.sv
[ 50%] Generating 1_lsu_stbuf.sv
[ 56%] Generating 2_ahb_to_axi4.sv
[ 6%] Generating 15_exu.sv
[ 12%] Generating 16_dec_decode_ctl.sv
[ 25%] Generating 12_beh_lib.sv
[ 25%] Generating 14_mem_lib.sv
[ 31%] Generating 2_ahb_to_axi4.sv
[ 37%] Generating 13_ifu_mem_ctl.sv
[ 43%] Generating 1_lsu_stbuf.sv
[ 50%] Generating 10_lsu_bus_intf.sv
[ 56%] Generating 11_ifu_bp_ctl.sv
[ 62%] Generating 3_rvjtag_tap.sv
[ 68%] Generating 4_dec_tlu_ctl.sv
[ 75%] Generating 5_lsu_bus_buffer.sv
[ 81%] Generating 6_dbg.sv
[ 87%] Generating 6_dbg.sv
[ 87%] Generating 7_axi4_to_ahb.sv
[ 93%] Generating 8_ifu_aln_ctl.sv
[100%] Generating 9_tb_top.sv
Expand Down
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