Support Vecs of empty Bundles (backport #2543) (#2544)

* Support Vecs of empty Bundles (#2543)

(cherry picked from commit a1e3a6b)

* Handle differences between Chisel 3.4 and 3.5

Also a minor difference in Scala 2.11

Co-authored-by: Jack Koenig <koenig@sifive.com>

core/src/main/scala/chisel3/Aggregate.scala

@@ -178,8 +178,8 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
     }
 
     // Since all children are the same, we can just use the sample_element rather than all children
-    // .get is safe because None means mixed directions, we only pass 1 so that's not possible
-    direction = ActualDirection.fromChildren(Set(sample_element.direction), resolvedDirection).get
+    direction =
+      ActualDirection.fromChildren(Set(sample_element.direction), resolvedDirection).getOrElse(ActualDirection.Empty)
   }
 
   // Note: the constructor takes a gen() function instead of a Seq to enforce
@@ -254,6 +254,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
       case ActualDirection.Bidirectional(ActualDirection.Default) | ActualDirection.Unspecified =>
         SpecifiedDirection.Unspecified
       case ActualDirection.Bidirectional(ActualDirection.Flipped) => SpecifiedDirection.Flip
+      case ActualDirection.Empty                                  => SpecifiedDirection.Unspecified
     }
     // TODO port technically isn't directly child of this data structure, but the result of some
     // muxes / demuxes. However, this does make access consistent with the top-level bindings.

src/test/scala/chiselTests/Vec.scala

@@ -318,4 +318,26 @@ class VecSpec extends ChiselPropSpec with Utils {
   property("reduceTree should preserve input/output type") {
       assertTesterPasses { new ReduceTreeTester() }
   }
+
+  property("Vecs of empty Bundles and empty Records should work") {
+    class MyModule(gen: Record) extends MultiIOModule {
+      val idx = IO(Input(UInt(2.W)))
+      val in = IO(Input(gen))
+      val out = IO(Output(gen))
+
+      val reg = RegInit(0.U.asTypeOf(Vec(4, gen)))
+      reg(idx) := in
+      out := reg(idx)
+    }
+    class EmptyBundle extends Bundle
+    class EmptyRecord extends Record {
+      val elements = collection.immutable.ListMap.empty[String, Data]
+      override def cloneType = (new EmptyRecord).asInstanceOf[this.type]
+    }
+    for (gen <- List(new EmptyBundle, new EmptyRecord)) {
+      val chirrtl = ChiselStage.emitChirrtl(new MyModule(gen))
+      chirrtl should include("input in : { }")
+      chirrtl should include("reg reg : { }[4]")
+    }
+  }
 }