Shift right produce at least 1 width result

chipsalliance · Jan 20, 2024 · 47b8354 · 47b8354
1 parent 628f3d5
commit 47b8354
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Showing 2 changed files with 10 additions and 1 deletion.
diff --git a/core/src/main/scala/chisel3/Width.scala b/core/src/main/scala/chisel3/Width.scala
@@ -13,7 +13,7 @@ sealed abstract class Width {
   def max(that:              Width): Width = this.op(that, _ max _)
   def +(that:                Width): Width = this.op(that, _ + _)
   def +(that:                Int):   Width = this.op(this, (a, b) => a + that)
-  def shiftRight(that:       Int): Width = this.op(this, (a, b) => 0.max(a - that))
+  def shiftRight(that:       Int): Width = this.op(this, (a, b) => 1.max(a - that))
   def dynamicShiftLeft(that: Width): Width =
     this.op(that, (a, b) => a + (1 << b) - 1)
 

diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
@@ -211,6 +211,11 @@ class UIntLitZeroWidthTester extends BasicTester {
   stop()
 }
 
+class ShiftRightResultAtLeast1BitWidth extends BasicTester {
+  assert((0.U(32.W) >> 32).getWidth == 1)
+  stop()
+}
+
 class UIntOpsSpec extends ChiselPropSpec with Matchers with Utils {
 
   property("Bools can be created from 1 bit UInts") {
@@ -485,4 +490,8 @@ class UIntOpsSpec extends ChiselPropSpec with Matchers with Utils {
     chirrtl should include("connect y, a")
     chirrtl should include("connect z, b")
   }
+
+  property("Shift right should be result in at least 1 bit width") {
+    assertTesterPasses(new ShiftRightResultAtLeast1BitWidth)
+  }
 }