Support XMRs to Analog in D/I (backport #4181) (#4182)

* Support XMRs to Analog in D/I (#4181)

(cherry picked from commit 9ec0fa2)

# Conflicts:
#	core/src/main/scala/chisel3/experimental/Analog.scala

* Resolve backport conflict

---------

Co-authored-by: Jack Koenig <koenig@sifive.com>

core/src/main/scala/chisel3/experimental/Analog.scala

@@ -58,7 +58,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
     }
 
     targetTopBinding match {
-      case _: WireBinding | _: PortBinding | _: ViewBinding | _: AggregateViewBinding =>
+      case _: WireBinding | _: PortBinding | _: ViewBinding | _: AggregateViewBinding | CrossModuleBinding =>
         direction = ActualDirection.Bidirectional(ActualDirection.Default)
       case x => throwException(s"Analog can only be Ports and Wires, not '$x'")
     }

src/test/scala/chiselTests/experimental/hierarchy/Examples.scala

@@ -5,7 +5,7 @@ package chiselTests.experimental.hierarchy
 import chisel3._
 import chisel3.util.Valid
 import chisel3.experimental.hierarchy._
-import chisel3.experimental.BaseModule
+import chisel3.experimental.{attach, Analog, BaseModule}
 
 object Examples {
   import Annotations._
@@ -316,6 +316,13 @@ object Examples {
     out := in
   }
 
+  @instantiable
+  class HasAnalogWire extends RawModule {
+    @public val port = IO(Analog(8.W))
+    @public val wire = Wire(Analog(32.W))
+    attach(port, wire)
+  }
+
   class AddTwoNestedInstantiableData(width: Int) extends Module {
     val in = IO(Input(UInt(width.W)))
     val out = IO(Output(UInt(width.W)))
@@ -357,5 +364,4 @@ object Examples {
     out := copy.out
 
   }
-
 }

src/test/scala/chiselTests/experimental/hierarchy/InstanceSpec.scala

@@ -8,6 +8,7 @@ import chisel3._
 import chisel3.experimental.BaseModule
 import chisel3.experimental.hierarchy.{instantiable, public, Definition, Instance}
 import chisel3.util.{DecoupledIO, Valid}
+import chisel3.experimental.{attach, Analog}
 
 // TODO/Notes
 // - In backport, clock/reset are not automatically assigned. I think this is fixed in 3.5
@@ -188,6 +189,7 @@ class InstanceSpec extends ChiselFunSpec with Utils {
     }
     it("(1.k): should work for targets on definition to have correct circuit name") {
       class Top extends Module {
+
         val definition = Definition(new AddOneWithAnnotation)
         val i0 = Instance(definition)
       }
@@ -207,6 +209,20 @@ class InstanceSpec extends ChiselFunSpec with Utils {
         MarkAnnotation("~Top|Top/i0:HasTypeParams>blah".rt, "blah")
       )
     }
+    it("(1.m): should work on Analog wires") {
+      class Top extends Module {
+        val port = IO(Analog(8.W))
+        val definition = Definition(new HasAnalogWire)
+        val i0 = Instance(definition)
+        attach(port, i0.port)
+        mark(i0.wire, "blah")
+      }
+      val (chirrtl, annos) = getFirrtlAndAnnos(new Top)
+      annos.collect { case c: MarkAnnotation => c } should contain(
+        MarkAnnotation("~Top|Top/i0:HasAnalogWire>wire".rt, "blah")
+      )
+      chirrtl.serialize should include("attach (port, i0.port)")
+    }
   }
   describe("(2) Annotations on designs not in the same chisel compilation") {
     it("(2.a): should work on an innerWire, marked in a different compilation") {