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scaladoc groups
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mwachs5 committed Apr 21, 2022
1 parent fbe5129 commit 7994b88
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Showing 3 changed files with 17 additions and 0 deletions.
7 changes: 7 additions & 0 deletions src/main/scala/chisel3/util/Bitwise.scala
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,7 @@ object FillInterleaved {
*/
def apply(n: Int, in: UInt): UInt = macro SourceInfoTransform.nInArg

/** @group SourceInfoTransformMacro */
def do_apply(n: Int, in: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
_apply_impl(n, in.asBools)

Expand All @@ -37,6 +38,7 @@ object FillInterleaved {
*/
def apply(n: Int, in: Seq[Bool]): UInt = macro SourceInfoTransform.nInArg

/** @group SourceInfoTransformMacro */
def do_apply(n: Int, in: Seq[Bool])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
_apply_impl(n, in)

Expand Down Expand Up @@ -64,12 +66,14 @@ object PopCount {

def apply(in: Iterable[Bool]): UInt = macro SourceInfoTransform.inArg

/** @group SourceInfoTransformMacro */
def do_apply(in: Iterable[Bool])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = _apply_impl(
in.toSeq
)

def apply(in: Bits): UInt = macro SourceInfoTransform.inArg

/** @group SourceInfoTransformMacro */
def do_apply(in: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = _apply_impl(
(0 until in.getWidth).map(in(_))
)
Expand All @@ -95,6 +99,7 @@ object Fill {
*/
def apply(n: Int, x: UInt): UInt = macro SourceInfoTransform.nxArg

/** @group SourceInfoTransformMacro */
def do_apply(n: Int, x: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = {
n match {
case _ if n < 0 => throw new IllegalArgumentException(s"n (=$n) must be nonnegative integer.")
Expand Down Expand Up @@ -122,6 +127,7 @@ object Fill {
* }}}
*/
object Reverse {

private def doit(in: UInt, length: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
length match {
case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.")
Expand All @@ -144,5 +150,6 @@ object Reverse {

def apply(in: UInt): UInt = macro SourceInfoTransform.inArg

/** @group SourceInfoTransformMacro */
def do_apply(in: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = doit(in, in.getWidth)
}
2 changes: 2 additions & 0 deletions src/main/scala/chisel3/util/Cat.scala
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,7 @@ object Cat {
*/
def apply[T <: Bits](a: T, r: T*): UInt = macro SourceInfoTransform.arArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Bits](a: T, r: T*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
_apply_impl(a :: r.toList)

Expand All @@ -36,6 +37,7 @@ object Cat {
*/
def apply[T <: Bits](r: Seq[T]): UInt = macro SourceInfoTransform.rArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Bits](r: Seq[T])(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
_apply_impl(r)

Expand Down
8 changes: 8 additions & 0 deletions src/main/scala/chisel3/util/Reg.scala
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ object RegEnable {
*/
def apply[T <: Data](next: T, enable: Bool): T = macro SourceInfoTransform.nextEnableArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](next: T, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
val r = Reg(chiselTypeOf(next))
when(enable) { r := next }
Expand All @@ -31,6 +32,7 @@ object RegEnable {
*/
def apply[T <: Data](next: T, init: T, enable: Bool): T = macro SourceInfoTransform.nextInitEnableArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](
next: T,
init: T,
Expand Down Expand Up @@ -59,6 +61,7 @@ object ShiftRegister {
*/
def apply[T <: Data](in: T, n: Int, en: Bool): T = macro SourceInfoTransform.inNEnArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](
in: T,
n: Int,
Expand All @@ -82,6 +85,7 @@ object ShiftRegister {
*/
def apply[T <: Data](in: T, n: Int): T = macro SourceInfoTransform.inNArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T =
_apply_impl(in, n)

Expand All @@ -108,6 +112,7 @@ object ShiftRegister {
*/
def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T = macro SourceInfoTransform.inNResetDataEnArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](
in: T,
n: Int,
Expand All @@ -130,6 +135,7 @@ object ShiftRegisters {
*/
def apply[T <: Data](in: T, n: Int, en: Bool): Seq[T] = macro SourceInfoTransform.inNEnArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](
in: T,
n: Int,
Expand Down Expand Up @@ -158,6 +164,7 @@ object ShiftRegisters {
*/
def apply[T <: Data](in: T, n: Int): Seq[T] = macro SourceInfoTransform.inNArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](in: T, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Seq[T] =
_apply_impl(in, n)

Expand All @@ -170,6 +177,7 @@ object ShiftRegisters {
*/
def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T] = macro SourceInfoTransform.inNResetDataEnArg

/** @group SourceInfoTransformMacro */
def do_apply[T <: Data](
in: T,
n: Int,
Expand Down

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