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Add features.{LowerCaseNames, UpperCaseNames} transforms
Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add LowerCaseNames and UpperCaseNames transforms
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// See LICENSE for license details. | ||
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package firrtl.features | ||
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import firrtl.{analyses, Namespace, passes, Transform} | ||
import firrtl.options.Dependency | ||
import firrtl.stage.Forms | ||
import firrtl.transforms.ManipulateNames | ||
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/** Parent of transforms that do change the letter case of names in a FIRRTL circuit */ | ||
abstract class LetterCaseTransform extends ManipulateNames { | ||
override def prerequisites = Seq(Dependency(passes.LowerTypes)) | ||
override def optionalPrerequisites = Seq.empty | ||
override def optionalPrerequisiteOf = Forms.LowEmitters | ||
override def invalidates(a: Transform) = a match { | ||
case _: analyses.GetNamespace => true | ||
case _ => false | ||
} | ||
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protected def newName: String => String | ||
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final def condition = _ => true | ||
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final def manipulate = (a: String, ns: Namespace) => newName(a) match { | ||
case `a` => a | ||
case b => ns.newName(b) | ||
} | ||
} | ||
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/** Convert all FIRRTL names to lowercase */ | ||
final class LowerCaseNames extends LetterCaseTransform { | ||
override protected def newName = (a: String) => a.toLowerCase | ||
} | ||
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/** Convert all FIRRTL names to UPPERCASE */ | ||
final class UpperCaseNames extends LetterCaseTransform { | ||
override protected def newName = (a: String) => a.toUpperCase | ||
} |
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