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Verilog integer literals cause VCS warnings #3

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aswaterman opened this issue Aug 4, 2015 · 1 comment
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Verilog integer literals cause VCS warnings #3

aswaterman opened this issue Aug 4, 2015 · 1 comment
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@aswaterman
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Leading zeros on UInt constants should be stripped to avoid lint errors (e.g. emit 4'h2 instead of 4'h02).
@aswaterman
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Moving this to FIRRTL.

seldridge added a commit that referenced this issue Apr 6, 2022
@seldridge
Merge pull request #3 from sifive/dev/seldridge/sonatype-publish
92041a5 
Add publishing to sonatype
@mwachs5 mwachs5 mentioned this issue Jun 2, 2023
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@aswaterman