when statement is incorrectly synthesized

[aswaterman]

Failing input: http://www.eecs.berkeley.edu/~waterman/whenBug.fir

The following code snippet

reg out_slow_bits : UInt<17>, clock, reset
out_slow_bits := tohost_q.deq.bits
when fromhost_q.deq.valid :
  out_slow_bits := fromhost_q.deq.bits

generates the following incorrect Verilog:

always @(posedge clock) begin
  out_slow_bits <= fromhost_q$deq$bits;
end

Of course, the correct code is

always @(posedge clock) begin
  out_slow_bits <= fromhost_q$deq$valid ? fromhost_q$deq$bits : tohost_q$deq$bits;
end

[aswaterman]

Moving this to FIRRTL.