This repository contains a Python library and utilities for working with
"Routing Resource Graph" (rr-graph
) files
used by F4PGA and
Verilog to Routing.
It supports both the XML and
Cap'n'Proto formats of rr-graph
files.
The Cap'n'Proto schema is generated from the
XML schema @ vtr-verilog-to-routing/vpr/src/route/rr_graph.xsd
using the uxsdcxx tool.
For information on the schema generation can be found in the
SCHEMA_GENERATOR.md
file in Verilog to Routing.
A full contribution guide can be found in docs/contributing.md
.
A few important points;
-
All contributions should be sent as GitHub Pull requests.
-
By contributing you agree to the code of conduct.
-
All commits are required to include a DCO sign off line.
All software (code, associated documentation, support files, etc) in this repository is licensed under the very permissive Apache-2.0 Licence.
A copy can be found in the LICENSE
file.
All new contributions must also be released under this license.
pip install rr-graph
FYI: Builds are automatically published to GitHub on every push to this repository.
pip install git+https://github.com/chipsalliance/f4pga-rr-graph.git#egg=rr-graph
python setup.py install
or python setup.py develop
To setup a local development environment use the make venv
target which will
build you a Python virtualenv (in the
venv
directory) with the needed packages and tools.
The make version
target will output the current version of the rr-graph
library.
To run the tests, run make test
.
If you have an issue with the CI disagreeing with the output of your local
make test
output, you can also try the make test-like-ci
target to closer
match how the CI system runs the tests.
To run automated formatting over the repository, use make format
.
The make format-gha
target will update the GitHub Actions under
.github/workflows
with the latest version of the
included tasks.
It is recommended that you commit these updates separately from your other changes.