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Add SuggestSeqMemName annotation to rename replaced blackboxes #2404
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Add SuggestSeqMemName annotation to rename replaced blackboxes #2404
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This looks great! Just a couple of minor nits
As an alternative approach... would it make sense to just keep the user-provided name of the memory for the blackbox and change the name of the |
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
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does this change the instance names as well as the module names?
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As an alternative approach... would it make sense to just keep the user-provided name of the memory for the blackbox and change the name of the blackbox that gets generated?
@seldridge can you clarify this? You referred to the name of the blackbox twice.
does this change the instance names as well as the module names?
@mwachs5 great question, @jared-barocsi see my new comment on the test
The main goal here is that we want to be able to prefix the names of the modules that are creates by ReplSeqMems, it also seemed like some user control over the naming made sense. We want this to compose with a built-in prefixing API in Chisel3 so maybe some feedback in that context would be helpful as well.
val mems = Set( | ||
MemConf("renamed_mem", 7, 16, Map(WritePort -> 1, ReadPort -> 1), None) | ||
) | ||
val confLoc = "ReplSeqMemTests.confTEMP" | ||
val annos = Seq( | ||
ReplSeqMemAnnotation.parse("-c:CustomMemory:-o:" + confLoc), | ||
SuggestSeqMemNameAnnotation( | ||
CircuitTarget("CustomMemory") | ||
.module("CustomMemory") | ||
.ref("mem_0"), | ||
"renamed_mem" | ||
) | ||
) | ||
val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm, annos)) | ||
checkMemConf(res, mems) | ||
} |
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This test is showing the memory name in MemConf
, but it would be really helpful if it could also show what the instance and module names are for the wrapper module, as well as the instance of the blackbox.
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is the goal to change the instance name? I dont think in general we want to, but what it was doing before that the instance name was the same as the blackbox name... which IMHO is strange but that's the existing behavior
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I would say we do not want to change the instance name
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I guess by "change" there is "same as it was before this PR" or "change based on what the person passes in"... which do you mean we do NOT want to do
@jackkoenig wrote:
Ack. Fixed above. It seems like a cleaner API is to have the memory blackbox inherit the name of the original memory ( |
I think this is a reasonable suggestion, but it either doesn't fulfill the intended use case or would be a bit weird. The Prefixing API needs to make sure that all modules use the prefix, so this includes both the wrapper module and the blackbox. Using your suggestion, that means Chisel would have to give the prefix to the instance name of the memory which is a bit odd, I think that should still be derived from the name of the This is, of course, dancing around the need for packages/namespaces, and it's basically a huge pain that we can prefix all modules in Chisel (via chipsalliance/chisel#2155) but then ReplSeqMems decides to just screw everything up. |
We should NOT give the prefix to the instance name of the memory. |
…irrtl into replseqmem-suggest-names
This PR implements an annotation (
SuggestSeqMemNameAnnotation
) to rename a memory blackbox to a user-specified name instead of the default{mem name}_ext
.Contributor Checklist
Type of Improvement
API Impact
No new API
Backend Code Generation Impact
Memory blackboxes get renamed with th
Desired Merge Strategy
Squash and merge
Release Notes
Implement a mechanism to rename blackboxes generated by
ReplSeqMems
with a user-specified nameReviewer Checklist (only modified by reviewer)
Please Merge
?