Add Interchange tests for LIFCL-40

Signed-off-by: Robert Szczepanski <rszczepanski@antmicro.com>
chipsalliance · Oct 6, 2022 · 5e7ea30 · 5e7ea30
1 parent f16f5d5
commit 5e7ea30
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diff --git a/assets/boards.yaml b/assets/boards.yaml
@@ -42,6 +42,10 @@ lifcl-40:
  family: nexus
  device: LIFCL-40
  package: 9BG400C
+lifcl-40-QFN72:
+ family: nexus
+ device: LIFCL-40
+ package: QFN72
 lifcl-17:
  family: nexus
  device: LIFCL-17

diff --git a/assets/project/oneblink.yaml b/assets/project/oneblink.yaml
@@ -16,6 +16,7 @@ vendors:
  - icebreaker
  lattice-nexus:
  - lifcl-40
+ - lifcl-40-QFN72
  - lifcl-17
  - lifcl-17-WLCSP72
  quicklogic:

diff --git a/assets/vendors.yaml b/assets/vendors.yaml
@@ -27,6 +27,7 @@ lattice-ice40:
 lattice-nexus:
  boards:
  - lifcl-40
+ - lifcl-40-QFN72
  - lifcl-17
  - lifcl-17-WLCSP72
  toolchains:

diff --git a/src/oneblink/constr/lifcl-40-QFN72.xdc b/src/oneblink/constr/lifcl-40-QFN72.xdc
@@ -0,0 +1,7 @@
+set_property LOC L13 [get_ports clk]
+set_property LOC G19 [get_ports out]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports out]
+
+create_clock -name clk -period 13.333 [get_ports clk]