Skip to content

Commit

Permalink
add netv2 PCIe video example
Browse files Browse the repository at this point in the history
Signed-off-by: Wojciech Tatarski <wtatarski@antmicro.com>
  • Loading branch information
wtatarski committed Apr 30, 2020
1 parent 90e47fa commit 79a72f0
Show file tree
Hide file tree
Showing 48 changed files with 72,444 additions and 0 deletions.
56 changes: 56 additions & 0 deletions project/netv2-pcie.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,56 @@
{
"srcs": [
"third_party/vexriscv-verilog/VexRiscv_Lite.v",
"third_party/litepcie/litepcie/phy/xilinx_s7_x1/pcie_s7_x1_support.v",
"third_party/litepcie/litepcie/phy/xilinx_s7_x1/pcie_pipe_clock.v",
"src/netv2-pcie/top.v",
"src/netv2-pcie/pcie_s7_x1.v",
"src/netv2-pcie/pcie_s7_x1_pcie_top.v",
"src/netv2-pcie/pcie_s7_x1_pcie_pipe_pipeline.v",
"src/netv2-pcie/pcie_s7_x1_pipe_sync.v",
"src/netv2-pcie/pcie_s7_x1_gtp_pipe_rate.v",
"src/netv2-pcie/pcie_s7_x1_gtp_pipe_drp.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_rx.v",
"src/netv2-pcie/pcie_s7_x1_pcie2_top.v",
"src/netv2-pcie/pcie_s7_x1_pipe_reset.v",
"src/netv2-pcie/pcie_s7_x1_pcie_bram_7x.v",
"src/netv2-pcie/pcie_s7_x1_pipe_drp.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_tx.v",
"src/netv2-pcie/pcie_s7_x1_pipe_eq.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_top.v",
"src/netv2-pcie/pcie_s7_x1_pcie_pipe_lane.v",
"src/netv2-pcie/pcie_s7_x1_pcie_brams_7x.v",
"src/netv2-pcie/pcie_s7_x1_qpll_drp.v",
"src/netv2-pcie/pcie_s7_x1_gtp_cpllpd_ovrd.v",
"src/netv2-pcie/pcie_s7_x1_gt_wrapper.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_tx_pipeline.v",
"src/netv2-pcie/pcie_s7_x1_rxeq_scan.v",
"src/netv2-pcie/pcie_s7_x1_qpll_wrapper.v",
"src/netv2-pcie/pcie_s7_x1_gtp_pipe_reset.v",
"src/netv2-pcie/pcie_s7_x1_gtx_cpllpd_ovrd.v",
"src/netv2-pcie/pcie_s7_x1_pipe_user.v",
"src/netv2-pcie/pcie_s7_x1_gt_rx_valid_filter_7x.v",
"src/netv2-pcie/pcie_s7_x1_pipe_rate.v",
"src/netv2-pcie/pcie_s7_x1_core_top.v",
"src/netv2-pcie/pcie_s7_x1_qpll_reset.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_rx_pipeline.v",
"src/netv2-pcie/pcie_s7_x1_pcie_bram_top_7x.v",
"src/netv2-pcie/pcie_s7_x1_pcie_pipe_misc.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_rx_null_gen.v",
"src/netv2-pcie/pcie_s7_x1_pipe_wrapper.v",
"src/netv2-pcie/pcie_s7_x1_gt_common.v",
"src/netv2-pcie/pcie_s7_x1_pcie_7x.v",
"src/netv2-pcie/pcie_s7_x1_axi_basic_tx_thrtl_ctl.v",
"src/netv2-pcie/pcie_s7_x1_gt_top.v",
"src/netv2-pcie/xpm_cdc_single.v",
"src/netv2-pcie/prim_xilinx_ram_1p.v"
],
"top": "top",
"name": "netv2-pcie",
"data": [
"src/netv2-pcie/mem.init",
"src/netv2-pcie/mem_1.init",
"src/netv2-pcie/mem_2.init",
"src/netv2-pcie/edid_mem.init"
]
}
Loading

0 comments on commit 79a72f0

Please sign in to comment.